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Old 21st August 2012, 09:00 PM   #981
Zen Mod is offline Zen Mod  Serbia
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Quote:
Originally Posted by Antoinel View Post
ZM. I agree. The upper JFET will cuttoff after Vo exceeds the fixed dc value of bias if/when referenced to ground .
don't be so sure



(it's gate is bootstrapped )
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Old 21st August 2012, 09:49 PM   #982
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Quote:
Originally Posted by Zen Mod View Post
don't be so sure



(it's gate is bootstrapped )
ZM: I often have uncertainty. Pls take a look at post #38 and the schematic therein. The bias scheme for the upper bjt is bootstrapped to Vo, and thus float up and down with it.

ihquam. Will it help to see on the scope sine signals in addition to square?
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Old 21st August 2012, 09:56 PM   #983
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different ways of doing same thing , I mean your example and F6 itself

let's stick to one particular scheme of F6 and comment

whatever way of biasing you choose , gate will float along with it's secondary winding , and bias net will empower in absence of AC signal
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Old 21st August 2012, 10:18 PM   #984
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Quote:
Originally Posted by Zen Mod View Post
R1*C5 doesn't have any special relation , at least not for me ;

and that scenario of xformer loading was just one of several , which I already mentioned

which one you'll decide to pursue , is up to you

all will lead to same result - proper loading of secondary , proper gate feed , stable bias
I changed R12 and R13 back to 47K and added 100K pots across the secondaries and adjusted the pots to minimize THD at 40Hz. The minimum occurred at very low values: 409 ohms across the upper fet, and 900 ohms across the lower fet. Is this believable? Here is the resulting THS vs Freq sweep. The loading made only a minor reduction in the THD at low frequencies.
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Old 21st August 2012, 10:35 PM   #985
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good ; everything believable

now just wait for Pa's article and observe THD spectra which he chose

I'm dumb , so I'll not precognition anything

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Old 22nd August 2012, 12:40 AM   #986
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lhquam,

i. Re post 984. The loading of the tx secondaries is to flatten the peak we sometimes see at the top end. If your freq response is already flat, then you would not normally need it. Indeed, in the specs for various signal transformers, manufacturers sometimes specify termination resistance and sometimes they do not. The technical paper on Jensens site has a good discussion on this.

ii. Re my questions on gain and feedback. I'm not suggesting that your scheme is incorrect. However, for this topology as Antoinel, NP and a few others have pointed out, it is crucial that the top and bottom fets see the exact same conditions. I found that this was difficult to do easily. In many of the configs I tried, I ended up with the top and bottom halves contributing differing gain amounts. The effect was only visible open loop with any potential local fb loops eliminated (ie transformer is bypassed for the 'dead' fet + battery bias for the same, no global fb) Tedious - agreed but it seems really worthwhile to nail this correctly lest we end up with a transformer input JLH in disguise. When I gave the [edit:] gate of top fet any lowish resistance return to ground, its gain changed, indicating a local fb loop. In your example, reducing R12 & R13 increased local fb & caused reduced thd. Overall gain might not change much though - as we all know that's one of the key 'contributions' of nfb - to dampen the effect of gain variations in the amplifying blocks towards the systems total gain.

iii) In the event that this line of thinking interests you, might I offer two suggestions ?

a) You can minimise the local fb (if that is your desire) by increasing the resistance in the biasing network (see F1 service manual http://www.firstwatt.com/pdf/prod_f1_srv.pdf for an example). It might be the case that the resistors are already high enough in value and therefore all is well but worth noting that NP used 27k with the R100s but it had to go as high as 0.5M with the IRF parts ! I don't know if 27k is [edit:] high enough (with gate stoppers at 22R) but there's only one way to find out for sure.

b) Whatever biasing network etc you end up with, its worth measuring the top and bottom halves gain as described in (ii) above to ensure that you're getting what you expect. If the two gains are materially different: rinse, wash & repeat

Interesting thread .....

Last edited by kasey197; 22nd August 2012 at 12:50 AM.
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Old 22nd August 2012, 12:48 AM   #987
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Quote:
Originally Posted by flg View Post
I'm not convinced there is voltage gain from the top FET? The input is G-S, the output is the Source. It's Common Drain/Source follower
my vote is for

Would that put your calculation results where you think they should be?
flg, I, like you, took a while to be convinced, but did some thinking and agreed that it did in fact provide current/voltage gain in common source mode. Simple experiments as posted on #561 in this thread showed that was the case as well.
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Old 22nd August 2012, 01:39 AM   #988
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kasey197: Your schematic in post #161 shows that the bias for the upper JFET is referenced to the output node. It rides up and down with the output signal Vo. The upper JFET is always in Class A.
ihquam: Your schematic in post #941 shows that the bias for the upper JFET is referenced to ground instead. The gate-source junction of the upper JFET will reverse bias as Vo goes positive relative to ground. The upper JFET can cut-off and switch to Class B

The two biasing schemes above are different with different operational outcomes: I am not sure whether my read is correct. But; which of the two biasing schemes do you think is in the actual design of Mr. Pass? I have a preference to that of kasey197.
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Old 22nd August 2012, 02:15 AM   #989
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sorry in advance for a dumb question !

I remember reading Nelson's article on negative feedback, it left a lasting impression on me. There are many benefits to avoiding negative feedback. And when a transformer is in the loop it adds it's own challenges. So if this circuit has -ve feedback I am curious as to why ?
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Old 22nd August 2012, 02:20 AM   #990
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Quote:
Originally Posted by Antoinel View Post
kasey197: Your schematic in post #161 shows that the bias for the upper JFET is referenced to the output node. It rides up and down with the output signal Vo. The upper JFET is always in Class A.

which of the two biasing schemes do you think is in the actual design of Mr. Pass?
>>Naw I dont find that. Vgs for upper fet = variable signal voltage across tx sec + fixed vgs bias voltage. Second term is only 1.x V. Upper fet switches off ultimately and we move into class B. Experimentally, for the R100s and using the biasing scheme mentioned above, I see clipping (by that I mean 1% thd) at 44V RMS across at 6.8R load = 140Wrms with +/-24 V rails. Thats way beyond what the 1.6A bias can support into class A.

>>Dunno and I think either works ok provided we dimension the resistances accordingly. Which one he chooses will depend as always on the magic of the operating points chosen which we cannot guess. There are somethings though that we CAN guess with some amount of certainty:

a) PASS = Performance Amplification through Sophisticated Simplicity {Da Vinci said that simplicity is the ultimate sophistication ...}

b) If some funky fb trick is used (see Watts New update from long ago0, then perhaps we'll see high-z bias network to reduce/eliminate local fb and caps in series with the tx primary.

c) If fb is as is shown on the conceptual schema and tx is set for 1:1, then I'd guess low-z bias network with local and global fb. This is the scheme he used in ZV5.

I guess we can play with some of these variations ourselves. I can follow a recipe fairly closely but can never replicate a dish exactly. If we have just an idea of some of the ingredients, our results will unlikely even be close

Last edited by kasey197; 22nd August 2012 at 02:23 AM.
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