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Old 21st August 2012, 06:06 PM   #971
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flg: kasey197 wrote in post #959 the following

We can see that a 0.5V change in vgs causes Ids to change by 5 to 7 amps depending on vgs. Taking the worst case of 5, this implies transconductance of 5/0.5 = 10S. But the fets transconductance we derived from above observed results (after taking care to correct for source degeneration rs) gives us a measured value of only 4.7 S.




The underlined are real values from the graph kasey197 posted. I used them below to answer your specific question regarding the voltage gain of the upper FET.
  • Io= 5 Amperes.
  • Vo = 5 Amperes multiplied by Load resistance [ 4 Ohms] = 20 V. I chose 4 Ohms so the calculated Vo is less than a hypothetical positive rail of 25 V [no clipping]. If I chose 8 Ohms instead, then the positive rail voltage is 50 V.
  • Av= Vo/Vi = 20/0.5 = 40
The answer to your question is: the upper JFET has voltage gain.
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Old 21st August 2012, 06:45 PM   #972
lhquam is offline lhquam  United States
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Quote:
Originally Posted by Zen Mod View Post
few things:
-toss out that input cap
-put some caps to gnd , after those 1K5 resistors in input buffer's drains
I modified from my circuit shown in post 941 as follows: R5 changed to 100K. C5 and C6 have been increased to 62uf (15uf || 47uf). R12 and R15 decreased to 15K. I found that THD decreased by making R12 and R15 smaller.

Here are THD vs frequency sweeps with and without the input cap.
The first plot is with input cap, the second without. As you can see, the input cap doesn't seem to degrade things.
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File Type: jpg F6a-fsweep2-cap.jpg (125.0 KB, 319 views)
File Type: jpg F6a-fsweep2-no-cap.jpg (123.6 KB, 306 views)
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Old 21st August 2012, 06:57 PM   #973
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flg: you wrote above:

Whoa! Simultaneous output voltage=8, where did that come from????? the Drain might have 8V because somehow the upper FET has 8Vgs when only fed by.5? But, you might as well put a resistor inplace of the Bottom FET??? If the top FET has 8V on it's Source and the Bottom FET is "OFF", You must have only a 10V rail and your clipping.

We hopefully agree that both JFETs are matched, and so are the signals to them but; with opposite phase [this debate was over] per Mr. Pass. A positive Vgs happens at the upper JFET, and a simultaneous, and equal negative Vgs happens at the lower JFET. Thus, the channel of the upper JFET opens further and passes additional current through it. By contrast, the channel of the lower JFET closes and removes the same value of pre-existing current flowing through it. The upper JFET has a non-inverting gain of Av [previous post]. The bottom JFET must also have a simultaneous inverting gain of the absolute value of Av. There can only one unique value of output voltage which is Av due to strict matching. The operation of the bottom JFEt is exactly the opposite [closes] as the upper one [opens];clearly noting that the two matched JFETs are operating along a linear Class A trajectory.

If one did not know ahead of time that we're talking about 2 JFETs per the topology of Conceptual F6, one may conclude this [black box] to be one single JFET operating in Class A with a non-inverting gain of Av.

Last edited by Antoinel; 21st August 2012 at 07:10 PM.
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Old 21st August 2012, 07:12 PM   #974
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Quote:
Originally Posted by lhquam View Post
I modified from my circuit shown in post 941 as follows: R5 changed to 100K. C5 and C6 have been increased to 62uf (15uf || 47uf). R12 and R15 decreased to 15K. I found that THD decreased by making R12 and R15 smaller.

Here are THD vs frequency sweeps with and without the input cap.
The first plot is with input cap, the second without. As you can see, the input cap doesn't seem to degrade things.
regarding R12 & R15 - xactly as I told you - you need to find appropriate loading for xformer

regarding input cap - you hear difference ..... or not ; but you'll hardly measure that difference
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Old 21st August 2012, 07:14 PM   #975
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Quote:
Originally Posted by Antoinel View Post
flg: kasey197 wrote in post #959 the following
We can see that a 0.5V change in vgs causes Ids to change by 5 to 7 amps depending on vgs. Taking the worst case of 5, this implies transconductance of 5/0.5 = 10S. But the fets transconductance we derived from above observed results (after taking care to correct for source degeneration rs) gives us a measured value of only 4.7 S.
What he is talking about is a data sheet Vds vs Ids graph. The S is grounded. The gate is fed a constant voltage ref to gnd, and the Vds is sweeped. To save alot of typing, there is no floating Source and Gate Drive like the F6 top FET
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Old 21st August 2012, 07:20 PM   #976
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Disconect the xfrmr from the top FET and tell me what kind of gain you have?
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Old 21st August 2012, 08:10 PM   #977
lhquam is offline lhquam  United States
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Quote:
Originally Posted by Zen Mod View Post
regarding R12 & R15 - xactly as I told you - you need to find appropriate loading for xformer

regarding input cap - you hear difference ..... or not ; but you'll hardly measure that difference
Can the transformer be "optimally" loaded by putting the appropriate resistor across the secondary winding and using the high R resistor (R12 and R13) for the bias voltage? That has the advantage of increasing the time constant of R1*C5. I briefly experimented with that, but probably didn't use the right values for loading.
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Old 21st August 2012, 08:19 PM   #978
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Quote:
Originally Posted by flg View Post
Disconect the xfrmr from the top FET and tell me what kind of gain you have?
flg: Like you and others, I hope that Mr. Pass explains its operation using verbiage and equations.

N.B. I failed to mention in my earlier post the following. For the upper JFET, the AC signal from the transformer's secondary rides atop [or floats above] the output signal Vo in real time, and is in phase with it. It is like two AC generators or batteries connected in series. Some may call it bootstrapping? Thus, the upper JFET will always have an AC signal [from the transformer secondary only] between its gate and source and a Vds [positive rail minus Vo+] to operate. In my opinion, the upper JFET uses these two essential variables to deliver a variable output current.

The underlined may further suggest that the bias circuit for the upper JFET needs to be connected to the output rather than to ground; so it also rides up and down on top of Vo like the concurrent AC signal. This bias scheme is clearly shown in OTLAmp1.pdf of post #38. Otherwise, the upper JFET will get cutoff if its bias circuit is referenced to ground!

Last edited by Antoinel; 21st August 2012 at 08:46 PM.
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Old 21st August 2012, 08:20 PM   #979
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R1*C5 doesn't have any special relation , at least not for me ;

and that scenario of xformer loading was just one of several , which I already mentioned

which one you'll decide to pursue , is up to you

all will lead to same result - proper loading of secondary , proper gate feed , stable bias
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Old 21st August 2012, 08:56 PM   #980
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Quote:
Originally Posted by Zen Mod View Post
upper half bias doesn't need to go to gnd , but output rail

besides that , try to implement "those" few things in second iteration , then hear and measure difference
ZM. I agree. The upper JFET will cuttoff after Vo exceeds the fixed dc value of bias if/when referenced to ground .
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