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Old 18th August 2012, 11:40 PM   #881
buzzforb is offline buzzforb  United States
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Perhaps this would be of interest to some.

http://www.diyaudio.com/forums/solid...l-mosfets.html

It introduces a new problem to consider...offset control.
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Old 19th August 2012, 12:00 AM   #882
Antoinel is offline Antoinel  United States
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[QUOTE=buzzforb;3131845]Perhaps this would be of interest to some.

http://www.diyaudio.com/forums/solid...l-mosfets.html

It introduces a new problem to consider...offset control.[/QUOTE]

Interesting schematic in the link above. It shows a step-down transformer [4:1], and a capacitor in series with the secondary winding to block dc emanating from the simple resistor string divider used for bias.

The underlined may suggest using an output capacitor to block dangerous [to the load] levels. Is there a reason against using a mono-polar power supply [and thus a blocking output capacitor like in OTLAmp1] instead of a split + and - voltage rails? Some of the amps by Mr. Pass use output blocking caps; e.g. the recent ACA#1.
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Old 19th August 2012, 12:01 AM   #883
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these critters are more stable than mosfets

and Papa made M2 with complementary (verticals, not laterals !) mosfet output - stable as Dodo

so , me think that there is no problem , even with BA1 approach - most simple one
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Old 19th August 2012, 12:27 AM   #884
buzzforb is offline buzzforb  United States
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Now i got to set up rails so i can see what scaling output stage does.
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Old 19th August 2012, 07:38 AM   #885
triode_al is offline triode_al  Netherlands
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Quote:
Originally Posted by Antoinel View Post
Thank you Loudthud for your interesting analysis. It, and that of flg earlier now suggest that the upper FET is simply [and only] working as a modulated current source load to the bottom FET which is the [only] voltage gain device. Thus the math expression ZM used earlier relating voltage gain to the [bottom] FET's transconductance and load fits. This working scenario is palatable and digestible. I am happy.
As I see it both output FETS are voltage amplifiers.
  • The Xfmr generates a current in both devices in opposite phase.
  • Because they float, and the top one, not having a load on the Drain and not having a fixed Source, will dump the current that is being 'generated' by the gate modulation into the common out.
  • Both sides do that in parallel. . .
  • Without feedback, it is extreme high impedance.
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Old 19th August 2012, 12:12 PM   #886
Antoinel is offline Antoinel  United States
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Originally Posted by triode_al View Post
As I see it both output FETS are voltage amplifiers.
  • The Xfmr generates a current in both devices in opposite phase.
  • Because they float, and the top one, not having a load on the Drain and not having a fixed Source, will dump the current that is being 'generated' by the gate modulation into the common out.
  • Both sides do that in parallel. . .
  • Without feedback, it is extreme high impedance.
triode_al: I agree with you regarding the underlined, and the bullet items; but I am not sure about the last one on the extreme high impedance. Please refer to post #679 which is my newer understanding of the operation of the output stage of Conceptual F6. This understanding led me to propose a model shown in post #769, and a new thread which is entitled "Compound Power Amplifiers" in the Pass Labs Forum. The upper JFET is a voltage source amplifier [VSA] with gain. Its output current gain multiplied by the value of the load resistor is simplistically its voltage gain. It is universally accepted that the emitter port of a bjt, and the source port of a FET are intrinsically low impedance. Low is a relative term. The lower JFET is a current source amp or a transconductance amp [TCA]. It is also universally accepted that the collector of bjt and the drain of FET are high impedance ports. The output current gain of the lower JFET multiplied by the value of the load resistor is simplistically its voltage gain. The voltage gain from the upper JFET is equal to the voltage gain of the lower JFET; because of strict matching of the drive signals, and the JFETs. Thus; neither JFET drives current into the other. Each one appears as a very high impedance to the other; an impedance which is much higher than the value of the load resistor. So,their output voltage drives current only through the load.

The low output impedance [due only to the upper JFET] is then lowered further with loop feedback.
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Old 19th August 2012, 03:46 PM   #887
Nelson Pass is offline Nelson Pass  United States
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Quote:
Originally Posted by triode_al View Post
As I see it both output FETS are voltage amplifiers.
Operating Common-Source, they are both voltage and current amplifiers.

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Old 19th August 2012, 03:50 PM   #888
Antoinel is offline Antoinel  United States
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Originally Posted by Nelson Pass View Post
Operating Common-Source, they are both voltage and current amplifiers.

Thank you for the clarification.
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Old 19th August 2012, 03:59 PM   #889
buzzforb is offline buzzforb  United States
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Quote:
Originally Posted by Nelson Pass View Post
Operating Common-Source, they are both voltage and current amplifiers.

If drawn with the PSU, dont we see that both fets are passing signals through the PSU to the load, sort of like a circlotron. That is why Kasey got double the gain of what a single fet would yield
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Old 19th August 2012, 10:09 PM   #890
lhquam is offline lhquam  United States
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I think I have found a simple and very stable bias circuit for the F6.

I wired it up and made measurements. From 500Hz to 20KHz the THD behaves as one would expect. Below 500Hz, the THD increases in a highly erratic manner. See the figures below.

All tests were with 8 ohm load, 1.3A bias and 25V rails.

The frequency sweep is at 1 watt.
The power sweep is at 1kHz.
The spectrum is at 1kHz and 1 watt.

I am temporarily withholding the schematic so that I do not spoil your fun.
Attached Images
File Type: jpg F6a-fsweep1.jpg (115.2 KB, 309 views)
File Type: jpg F6a-wsweep1.jpg (57.2 KB, 307 views)
File Type: jpg F6a-spectrum-1watt.jpg (65.9 KB, 303 views)
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