One bias current sense resistor in addition to measuring Vout offset should be enough. I have seen absolutely no problems with bias instability for any values of Rs between 0R12 and 1R. I haven't yet tried Rs=0R0, but I expect it to be fine.
BTW: I just ran calculations for Z0 and DF with the source degeneration removed. Z0=0R335, Df=23.9.
BTW: I just ran calculations for Z0 and DF with the source degeneration removed. Z0=0R335, Df=23.9.
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The calculation was done using LTSpice and measuring Vout with 8 ohm and 4 ohm loads. The calculation was shown in earlier posts by both me and ZM.
IN biasing up my output, I had one pot vlue way off from other. THe trafo did a phenominal job of keeping the bias consistent and stable, even at the expense of robbing the other half's bias circuit to do it. Bias you amp up again and intentionally throw off one half. Watch what happens. Also, doesnt Rs still have a stablizing effect on the output even if it is not included in the degeneration?
Elna Silmic love stopped partially in Pass Laboratories, in the SIT 2 and one also, there are Clarity Caps PWA (SITs) or Clarity Cap ESA (XP30) types. But of course there might be a special selection for Nelson and Wayne......
So triode_al might be right wishing no electrolyt in the crucial places....
Ok gotcha - got the measurement part down. What was interesting was the calculating bit - ie how to estimate open n close loop output impedance from MOSFET characteristic stats n curves....
Elna Silmic love stopped partially in Pass Laboratories, in the SIT 2 and one also, there are Clarity Caps PWA (SITs) or Clarity Cap ESA (XP30) types. But of course there might be a special selection for Nelson and Wayne......
So triode_al might be right wishing no electrolyt in the crucial places....
Nelson is more than happy interchanging between either polypropylene or Elna Silmic. But if it is not a Silmic put in a PP cap
lhquam. Will you consider a closed loop gain of 2-3 to further lower Zo? Will the FE be able to handle input signals 6 Vrms or higher? In the limit, what will the value of Zo be at a closed loop gain =1; provided Teaser-6 doesn't oscillate. Gotta push the envelope! Generous input signal levels are available per the opening paragraph of Mr. Pass in his article of B1. Best gain structure one could have!
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ya sure in verity of your explanation
besides that , any impression of sound between two variations ?
I presume better , with Rs not included in modulation path
Nope.ya sure in verity of your explanation
Just know i started to bias the thing up by adjusting lower half of circuit. Got way ahead of upper half. LED's started to dim and went out. Bias across both RS was same. Pulled the fets, tuned post to where both bias voltages were the same. popped the fets back in, turned up the variac, LED's back on and bias coming up slowly. this was seconf time this happened. Also did it on Lateral version.
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according to myexperience with SJEP's , for decent thermal all you need is few LED/diodes in bias circ , and usual (+25-30C) heatsink
I can bet that Pa is not using diodes at all
but , I'm mu about value of Rs in origigi F6 , there must be few things left , which old Fox count on , and we aren't even aware of
only logical explanation - that means that one output started to eat gate current , starving LED path
in case of plain resistor instead of CCS, situation will be different , at least slightly
Added insurance in the event a DIYer does not have the ideal heat sink. Mr. Pass has used thermistors in the past for best thermal management.
in that case ........ it's best that DIYer use fan .......... or , even better , fishing rod .
A CLG of 1 would be a bit extreme - the input JFETs would have to run at full rail voltages. CLG= 2 or 3 should be ok.
CLG=3 (actually 2.9) gives Zo=0R195 DF=41.
CLG=2 (actually 1.96) gives Zo=0R132, DF=60.6
CLG=3 (actually 2.9) gives Zo=0R195 DF=41.
CLG=2 (actually 1.96) gives Zo=0R132, DF=60.6
