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Old 21st June 2013, 11:19 AM   #4661
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Originally Posted by lhquam View Post
I received my F6CC Teaser boards and parts. Here is a picture of the build so far. Obviously the MOSFETs have not been yet attached with mica and grease. I am about ready for a smoke test.

This is a bench-test setup where the MOSFETs are attached using MOLEX connectors and elevated by a 1/4" aluminum plate which is attached to the heatsink with thermal grease and screws. This makes it easy to experiment with different MOSFETs be unscrewing them and readjusting the bias voltages. Also, using hex standoffs for power and output connections makes board removal easy in order to make component changes.
Will the heat sink be cooled by forced-air?
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Old 21st June 2013, 12:32 PM   #4662
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Will the heat sink be cooled by forced-air?
Assuming roughly F5 power dissipation, ie. 65 watts/channel, the heatsink should be adequate for convection cooling. It is from HeatsinkUSA: 10.8" wide, 7" long, and 2.5" fin height. 10.080" Wide Extruded Aluminum Heatsink - HeatsinkUSA, LLC Store
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Old 21st June 2013, 12:41 PM   #4663
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Have you considered a simple regulated cascode as a way of avoiding Rs? Would this allow a type of active degeneration of the cacode device, and with it, the fet it guards.
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Old 21st June 2013, 01:08 PM   #4664
lhquam is offline lhquam  United States
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Have you considered a simple regulated cascode as a way of avoiding Rs? Would this allow a type of active degeneration of the cacode device, and with it, the fet it guards.
As I have repeatedly stated, with the transformer secondaries connected to the MOSFET source pins, there is no AC degeneration, and the source resistor only affects DC bias stabilization. Same in the F6.

What you are suggesting could be accomplished in a simpler manner using a DC current servo in the gate bias circuit. Here is an example of a design for a cascoded F5 with no AC degeneration using a current servo:
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Old 21st June 2013, 01:25 PM   #4665
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way of avoiding Rs?
The F6 can be built without Rs affecting either AC degenration or DC bias. It would appear, that this is how Nelson chose to do it in his sample sent to 6moons. Clever control of the cascode could possibly accomplish this. I am new to the lingo, but i assume that a servo is the same as an error amplifier.
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Old 21st June 2013, 01:58 PM   #4666
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Originally Posted by lhquam View Post
Assuming roughly F5 power dissipation, ie. 65 watts/channel, the heatsink should be adequate for convection cooling. It is from HeatsinkUSA: 10.8" wide, 7" long, and 2.5" fin height. 10.080" Wide Extruded Aluminum Heatsink - HeatsinkUSA, LLC Store
Thanks lhquam for the valuable info.
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Old 21st June 2013, 02:00 PM   #4667
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Originally Posted by lhquam View Post
As I have repeatedly stated, with the transformer secondaries connected to the MOSFET source pins, there is no AC degeneration, and the source resistor only affects DC bias stabilization. Same in the F6.

What you are suggesting could be accomplished in a simpler manner using a DC current servo in the gate bias circuit. Here is an example of a design for a cascoded F5 with no AC degeneration using a current servo:
DC servo is a fascinating development; maybe a first to use an op amp in this thread or even the Pass Labs Forum.
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Old 21st June 2013, 02:19 PM   #4668
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thread most probably yes , forum not
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Old 21st June 2013, 02:37 PM   #4669
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A possible idea to stabilize the bias of the output stage will be to idle Q1 and Q2 at a lower current, and simultanously augment the needed total output current with [n] complementary current bootstraps; shown as bjts for example. This proposed circuit [attached] develops a constant voltage across Q1 and Q2 [your cascodes], and a simultaneous contant current flowing through them. This thinking was borrowed from US 4,107,619 which is STASIS[R] for the amps of Threshold Corp.

It is possible that this circuit may also function as a souped up F5!
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Old 22nd June 2013, 02:02 AM   #4670
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No smoke! The board layout appears to be fine, except that the pots are backwards wrt. clockwise increasing the relevant parameter (no big deal).

The overall bias current stability is fine, except that the output offset voltage drifts more than I would like. Is this problem related to the cascoded outputs? If so, there might be a simple 2-resistor solution based on negative feedback to the bias circuits.

The THD measurements are OK, but not as good as I am looking for. There is still a lot of tweaking to do.
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