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Old 30th July 2012, 05:36 PM   #441
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Quote:
Originally Posted by Antoinel View Post
My simplistic interpretation of the output stage is: The top FET has a voltage gain of 1 [common drain]. The bottom FET has a gain which is greater than 1 [common source].
Although the output is taken from the source of the upper FET, it is operating in common source mode because the winding driving it gets it's reference (AC wise) from the output (source). Since the windings float AC wise, both top and bottom FETs operate in the same mode. Any distortion caused by non-linearity of the top or bottom FET circuits will affect the output symmetrically causing odd order harmonics.
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Old 30th July 2012, 06:10 PM   #442
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Originally Posted by Loudthud View Post
Although the output is taken from the source of the upper FET, it is operating in common source mode because the winding driving it gets it's reference (AC wise) from the output (source). Since the windings float AC wise, both top and bottom FETs operate in the same mode. Any distortion caused by non-linearity of the top or bottom FET circuits will affect the output symmetrically causing odd order harmonics.
Thank you Loudthud for your interesting analysis. It, and that of flg earlier now suggest that the upper FET is simply [and only] working as a modulated current source load to the bottom FET which is the [only] voltage gain device. Thus the math expression ZM used earlier relating voltage gain to the [bottom] FET's transconductance and load fits. This working scenario is palatable and digestible. I am happy.
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Old 30th July 2012, 06:22 PM   #443
Zen Mod is offline Zen Mod  Serbia
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yup

output Jfet is either plain stupid or just careless - where load is connected ; all he cares/reflects is own internal impedance , as function of G vs. S modulation ;

considering this - both Jfets (lower and upper one ) are behaving in identical way ......... correctly speaking - exactly opposite way - meaning - while one is decreasing internal impedance , other one is increasing internal impedance in same amount ; just look at them as on two variable resistors , working unison in opposite directions .......... and you'll forget on all common source/drain/blahblah hogwash (I'm anyway unable to remember meaning of that "common S/D/G" nomenclature .... it just don't blend with my way of thinking )
as remainder - quasi complementary is , by function , same as complementary

I'm just (or "just" ) lacking in electronic vocabulary to express that
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Last edited by Zen Mod; 30th July 2012 at 06:30 PM.
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Old 30th July 2012, 06:25 PM   #444
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Originally Posted by Zen Mod View Post
yup

output Jfet is either plain stupid or just careless - where load is connected ; all he cares/reflects is own internal impedance , as function of G vs. S modulation ;

considering this - both Jfets (lower and upper one ) are behaving in identical way

as remainder - quasi complementary is , by function , same as complementary

I'm just (or "just" ) lacking in electronic vocabulary to express that
Thank you ZM. It all coming together.
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Old 30th July 2012, 06:26 PM   #445
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I thought ZM's math was regarding the reflected source impeadance seen by the output FETs looking back into the transformer?
Which I thought to be about 35 ohms or so from the buffer x (the turns ratio) ^2 (1) = 35 ohms not 75? The xfrmr and the FETs probably like that?
If you are going after some gain in the xfrmr, say 1:5.6, that would be 30 X (5.6^2) = 168 ohms. Now you are starting to see some source impeadance issues but, not really enough to worry about.
This was all predicated on the fact that I was thinking there was something like a B1 arrangement on the input and I thought that would be about 35 ohms. I't not. It's a complementary buffer. So whats the output impeadance of that? 17 ohms?
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Old 30th July 2012, 06:31 PM   #446
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@ Antoinel

........ blahblah ......... serve and protect

edited few lines above
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Old 30th July 2012, 06:33 PM   #447
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Originally Posted by flg View Post
I thought ZM's math was regarding the reflected source impeadance seen by the output FETs looking back into the transformer?
Sorry for injecting this confusion. ZM showed a thread even earlier than the one pertaining to the transformer [above] showing the relationship between the gain of a FET and its parameters plus load resistance etc. [e.g for for F5].
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Old 30th July 2012, 06:40 PM   #448
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Originally Posted by flg View Post
I thought,,,,,,,,,,
take it easy ;

what's output impedance of sole (say that load up is plain CCS ) buffer 2SJ74 ?

it's 1/S+Rs

what's load impedance of sole (say that load down is plain CCS) buffer 2SK170?

it's 1/S+Rs

so - when you have those two together , as complementary buffer - where each one is CCS to other one , you have output impedance as (1/S+Rs // 1/S+Rs) = (1/S+Rs)/2 , if we assume that S of both are ~ same

so - if you have , say , 50 Ohms of output impedance of buffer (lazy and don't remember S of sissy Toshiba's) , when output current capability is divided to 2 secondaries , it's logical that each secondary is seeing double that - 100 Ohms
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Last edited by Zen Mod; 30th July 2012 at 06:54 PM. Reason: ooked again what's up and what's down
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Old 30th July 2012, 06:51 PM   #449
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Quote:
Originally Posted by Zen Mod View Post
@ Antoinel

........ blahblah ......... serve and protect

edited few lines above
ZM: One liner replies may not be enough to teach DIYers and/or drive your point. Sometimes, the saying that Brevity is the soul of wit does not work well in/for technical matters. A clear math equation [like you showed earlier] may not cut it either. You pack a lot of technical/technology know-how. So please, be generous with your explanations; write, and write some more until there is no more for you to teach. You and us will feel enriched and satisfied in the end.
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Old 30th July 2012, 06:52 PM   #450
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I would think it is logical to look at 1 secondary and say 50 ohms (1:1+1) Or the other. But a 1:2 connection (both is series) is 200 ohms???
I guess now and then, now being now, other's are dumber than ZM
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