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Old 30th July 2012, 10:16 AM   #421
Zen Mod is offline Zen Mod  Serbia
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Default curiosity killed the cat - repeaters quality

just tested ( to refresh my weak memory) those repeater coils (pictured in one of my previous post)

exacttype is Iskra TL-1M , so called 600:600 , in fact 4 x 150R

two primaries connected in parallel , fed with siggene , 50 ohms tap

CRO across one secondary , loaded with 6K8 (estimated range of load in F6 )

it's 'ookin' linear 15Hz-58Khz , and up to 280Khz ;

there is some rise in few freqs between 58KHz and 180KHz , but nothing what appropriate RC loading can't handle

and they're primary made for telephone range

but do not forget some other wakoo implementations of telephone transmission lines - teleprinters and other crazy military purposes
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Old 30th July 2012, 10:18 AM   #422
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Quote:
Originally Posted by Antoinel View Post
What is the open loop gain of the proposed F6? Some of it needs to be sacrificed in order to lower intrinsic distortion and linearize the operation of the device.
I don't know did Pa chose lowish source resistor , or highish

let's wait to see what he chose - greater linearity or lower Rout
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Old 30th July 2012, 10:59 AM   #423
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Those repeater coils are expensive. Where do we find them other than FleaBay?
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Old 30th July 2012, 11:29 AM   #424
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Quote:
Originally Posted by Zen Mod View Post
I don't know did Pa chose lowish source resistor , or highish

let's wait to see what he chose - greater linearity or lower Rout
While we wait, we may analyze the schematic of simplified F6. Its front end is a complementary common drain configuration. Thus, it does not have voltage gain; but current gain. Is it correct to assume that the interstage transformer has a step-up voltage gain of 2? The output stage appears to have a voltage gain of 1. So the net open loop gain of the simplified F6 equals 2 or 6 dB [at best; from the transformer].
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Old 30th July 2012, 11:31 AM   #425
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dunno where , on your side of Big Splash

in fact - you have Jensens there
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Old 30th July 2012, 11:38 AM   #426
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Quote:
Originally Posted by Antoinel View Post
While we wait, we may analyze the schematic of simplified F6. Its front end is a complementary common drain configuration. Thus, it does not have voltage gain; but current gain. Is it correct to assume that the interstage transformer has a step-up voltage gain of 2? The output stage appears to have a voltage gain of 1. So the net open loop gain of the simplified F6 equals 2 or 6 dB [at best; from the transformer].
pretty much wrong , generally

input is Jfet voltage buffer

xformer is 1:1+1 (+ sign irrelevant for gain calc - take it as 1:1)

you can take output stage for calculations as sort of cascoded/double SE , so making gain calc as simple SE , then go from that (multiply with 2)

gain is simple - Rload/(1/S +Rs)

for more of same simple but effective logic - look at Pa's post here : Help with F5 with Gamut style MOSFET's
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Old 30th July 2012, 12:19 PM   #427
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Quote:
Originally Posted by Zen Mod View Post
pretty much wrong , generally

input is Jfet voltage buffer

xformer is 1:1+1 (+ sign irrelevant for gain calc - take it as 1:1)

you can take output stage for calculations as cascoded SE , so making gain calc as simple SE , then go from that

gain is simple - Rload/(1/S +Rs)

for more of same simple but effective logic - look at Pa's post here : Help with F5 with Gamut style MOSFET's
The calculation works for F5 because it has an output stage with opposed MOSFET drains. When the upper section is more on, the bottom section is relatively more off [high load impedance] and vice versa. In the simplified F6, the upper output FET is operating in the common drain configuration. We have learned the fundamental propertry of a source follower [upper FET] that it has voltage gain of 1! I will be surprised if you dispute this regardless of the math expressions you put forth. So the bottom FET must also generate a voltage gain of 1 to preserve the symmetry of the output signal.
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Old 30th July 2012, 12:46 PM   #428
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Consider for a moment that there is no top winding on the top FET. It is only a CCS, floating above a common Source gain stage. O.K.?
Now add the top winding... A small amount of signal, floating above the gain stage will be summed with the CCS. When the signal goes positive in the bottom secondary, the bottom FET turns on, higher current flows, the output swings low slightly more gain happens due to higher current! At the same time the signal is going negative in the top FET resisting the bottom FET slightly (reducing gain slightly).
When the signal in the bottom FET swings negative, the FET turns off and swings the output high. Somewhat less gain happens due to lower current. the top FET swings slightly higher due to some added signal from the top secondary, making up for the bottom FETs reduced gain????
Can anyone follow that???
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Old 30th July 2012, 01:44 PM   #429
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Quote:
Originally Posted by flg View Post
Consider for a moment that there is no top winding on the top FET. It is only a CCS, floating above a common Source gain stage. O.K.?
Now add the top winding... A small amount of signal, floating above the gain stage will be summed with the CCS. When the signal goes positive in the bottom secondary, the bottom FET turns on, higher current flows, the output swings low slightly more gain happens due to higher current! At the same time the signal is going negative in the top FET resisting the bottom FET slightly (reducing gain slightly).
When the signal in the bottom FET swings negative, the FET turns off and swings the output high. Somewhat less gain happens due to lower current. the top FET swings slightly higher due to some added signal from the top secondary, making up for the bottom FETs reduced gain????
Can anyone follow that???
Thank you for your explanation. Mr. Pass and/or ZM will reduce your language above [and mine below] into one or more equations; if not already done by ZM in an earlier thread. I do not have the skill to do so myself.

It follows from your discussion that simplified F6 can be easily and faithfully run in an open loop configuration. All elements, parameters and currents are symmetrical. What is loop feedback correcting for anyway if everything else is close to ideal to begin with?besides lowering Zout]. My simplistic interpretation of the output stage is: The top FET has a voltage gain of 1 [common drain]. The bottom FET has a gain which is greater than 1 [common source]. The load to the bottom FET load is the loudspeaker in parallel with the upper FET operating in the common gate configuration. Thus, the net output voltage into the loudspeaker is not symmetrical due to the different gain of the two FETs working the same loudspeaker. The resulting open loop gain [mostly from the bottom FET] is then partly sacrificed as loop feedback to restore output symmetry and purity; to a net voltage gain of 1. Loop feedback is forcing the voltage gain of the bottom FET down to 1. Or else distortion!
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Old 30th July 2012, 01:56 PM   #430
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Obviously I don't know the details of the circuit or Xfrmr so I am just guessing too! If all the windings are actually equal (1:1+1) that is a big hint. Is that true? Has NP actually agreed to that. 150 ohm, 600 ohm, or whatever?
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