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Old 30th November 2012, 10:58 PM   #3121
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I have yet to try the version with no degeneration, but i liked minimal degeration. When i rebuild mine, i will use the version woth no Rs on FE or output, possibly doubling up on onput jfets and adding cascoded bjt to FE, like ZM posted early.

Have you compared Onetics with Jensen?
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Old 30th November 2012, 11:17 PM   #3122
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I need to go back to the no degeneration version so as to maintain a baseline.
Relatively easy to switch.

Also might try what Nelson suggested in his article ( 0 and .05 ohms )

Multiple pairs sound interesting

Waiting for a board to do comparison between Jensen and Onetics - my hand wiring just isn't that good - I'm very slow

Separate note - FETs arrived thanks !!!!
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Old 30th November 2012, 11:52 PM   #3123
lhquam is offline lhquam  United States
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Another factor to consider beyond source degeneration is the effect due to unmatched R100 JFETs. My left channel appears to have very well matched JFETs and behaves much like LTSPICE simulations predict. In the right channel I have swapped around between 4 other R100s and cannot get simlar performance. The major difference is that the 3rd harmonic is much higher than with the left channel. The measured transconductances my R100s at 1.4A bias current do not appear to explain the behaviour that I am seeing. I am at a loss to explain why the 3rd harmonic differs so much.
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Old 1st December 2012, 05:40 AM   #3124
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Lhquam, don't mismatched fets result in H2 and not H3 ?
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Old 1st December 2012, 08:26 AM   #3125
generg is offline generg  Germany
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Quote:
Originally Posted by lhquam View Post
Another factor to consider beyond source degeneration is the effect due to unmatched R100 JFETs. My left channel appears to have very well matched JFETs and behaves much like LTSPICE simulations predict. In the right channel I have swapped around between 4 other R100s and cannot get simlar performance. The major difference is that the 3rd harmonic is much higher than with the left channel. The measured transconductances my R100s at 1.4A bias current do not appear to explain the behaviour that I am seeing. I am at a loss to explain why the 3rd harmonic differs so much.
My friend dsdjoy combined his 8 SS in all combinations in a MU follower arrangement. Out of 30 measured combinations only four delivered the wanted distortion spektra without change of the circuit design or Zen Pot.
So there seems to be much unsecurity in the results using these parts....May be you PM him.
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Last edited by generg; 1st December 2012 at 08:33 AM.
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Old 1st December 2012, 12:50 PM   #3126
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Quote:
Originally Posted by generg View Post
My friend dsdjoy combined his 8 SS in all combinations in a MU follower arrangement. Out of 30 measured combinations only four delivered the wanted distortion spektra without change of the circuit design or Zen Pot.
So there seems to be much unsecurity in the results using these parts....May be you PM him.
generg: A close look at the F6 finished product by Mr. Pass, shows the absence of user-adjustable Zen Pots on the front panel. The last picture of his article clearly shows the inside of F6. No Zen Pots therein either. The blue-turquoise parts are most probably the 5K pots to tweak bias and zero the output offset. It appears that Mr. Pass did not use Zen Pots.

Missing from the preceeding posts is via this question: What is the objective and subjective performance of one's diyF6 without Zen Pots? This is the baseline to introduce changes and determine their value on performance. I believe lhquam did some baseline characterization early on in his development; but quickly embraced using Zen Pots, and did not return to his baseline since.

N.B. Could the PCB be double-sided with 2 additional pots on the underside?

Last edited by Antoinel; 1st December 2012 at 01:03 PM.
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Old 1st December 2012, 01:59 PM   #3127
lhquam is offline lhquam  United States
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I think that differences between the internal source resistance of the FETs might explain the differences in H3.

Quote:
Originally Posted by kasey197 View Post
Lhquam, don't mismatched fets result in H2 and not H3 ?
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Old 1st December 2012, 03:56 PM   #3128
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Would this affect drain impedance, and along with it, the ability to use loadline cancellation as Nelson talks about.
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Old 1st December 2012, 04:20 PM   #3129
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Quote:
Originally Posted by lhquam View Post
I think that differences between the internal source resistance of the FETs might explain the differences in H3.
According to Mr. Pass, distortion in the dynamic sense emanates from a bjt, a FET etc. due to variation in its gain as it delivers power to the load. Variable gain is due to the changing current passing through the device and the changing voltage across its terminals as it does its job.

There is a high probability that Mr. Pass also characterizes the distortion characteristics of each power JFET, ans selects those which fit.



You have the skills and the tools to characterize the distortion of each power JFETin Teaser-6. For example:
  • Disable loop feedback
  • No load
  • Disconnect the secondary winding of the transformer's input to the bottom JFET
  • Connect its bias drive. The bottom JFET is now a constant current source to the upper JFET. The variable due to the current passing through the upper JFET [affecting its gain] is nulled.
  • Input signal [1KHz] at many output amplitudes to a peak value at +-20 V
  • Measure the distortion of the upper JFET due to variation of Vds.
  • Enable loop feedback and measure distortion at the same output levels used earlier.
  • Repeat all of the above using the lower JFET as the gain device and the upper JFET as its constant current load.
  • The constant current of 1.4 A at idle can be changed in the range of 0.4 A minimum to 2.4 A maximum to simulate 2 Ap-p delivered to the load . The linearity of the output signal is the outcome
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Old 1st December 2012, 06:02 PM   #3130
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The 1978 article by Mr. Pass which is entitled "Cascode Amp design" is a must read to understand and characterize the distortion of then a power NPN bjt. In our case, cascoding locks Vds to a constant value during operation but allows for current variations.

A possible idealized output amplifying device in a theoretical diyF6 maybe an NPN-STASIS (TM). It is made up of a power NPN transistor operating in Class A driving 4 or more PNPs. One set is needed for the upper and another identical set for the lower power output positions. However, the input impedance of each NPN is low compared to that of JFET. Nonetheless, this arrangement locks the variation of the current flowing through the input NPN in charge of defining net distortion to a constant.

I can envision replacing each on the NPNs operating in constant current mode with IRFP240s doing the same in a "clone STASIS (TM)"; clearly bending backwards to accomodate the diyF6 JENSEN.
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