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Old 1st October 2012, 06:22 PM   #2181
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look at FIG.4B , for instance

Input signal Vi is shown as positive starting voltage signal at base of Q1
that became negative starting Voltage signal on node 102

which means rising current signal through R4

which means rising voltage signal across R4
which means positive starting voltage signal for Q3 base
which means negative starting voltage signal at base of Q2

which means Q1 and Q2 are fed with antiphase signals on respective gates

which is exactly shown on FIG.3B

guyz will hear only difference between upper and lower Jfet modulation , having same-phase connected secondaris

which isn't even good for nulling adventures , what demands dynamic condition , not silent ones
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Last edited by Zen Mod; 1st October 2012 at 06:26 PM.
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Old 1st October 2012, 06:28 PM   #2182
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Quote:
Originally Posted by Zen Mod View Post
look at FIG.4B , for instance

Input signal Vi is shown as positive starting
that became negative starting V on node 102

which means rising current signal through R4

which means rising voltage signal across R4
which means positive starting voltage signal for Q3 base
which means negative starting voltage signal at gate of Q2

which means Q1 and Q2 are fed with antiphase signals on respective gates

which is exactly shown on FIG.3B
Please use the Aleph Current Source schematic as your example like I did. And goto Post #306; Mr. Pass said that in-phase drive worked; but ..
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Old 1st October 2012, 06:36 PM   #2183
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FIG.4B is Aleph CCS ;

same as FIG.1 , FIG.2 , FIG.3 , FIG.4A , FIG.4B , FIG.5

Pa's post #306 :

Quote:
Originally Posted by Nelson Pass View Post
Really, it was an honest mistake. The only mystery is how the circuit
worked so well that way...


..... what's that having with Aleph CCS patent ?

he obviously joked .....



besides that , with your misunderstanding of ALeph CCS patent ,you are implying that he deliberately twisted facts in his own patent , with intention of preventing scamers ?

which I have some difficulties to believe .....
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Old 1st October 2012, 06:57 PM   #2184
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Quote:
Originally Posted by Zen Mod View Post
FIG.4B is Aleph CCS ;

same as FIG.1 , FIG.2 , FIG.3 , FIG.4A , FIG.4B , FIG.5

Pa's post #306 :




..... what's that having with Aleph CCS patent ?

he obviously joked .....


besides that , with your misunderstanding of ALeph CCS patent ,you are implying that he deliberately twisted facts in his own patent , with intention of preventing scamers ?

which I have some difficulties to believe .....
I have a great respect for Mr. Pass, you, and the rest of DIYers. Fortunately, I am not implying anything.
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Old 1st October 2012, 10:52 PM   #2185
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Default F6 Decoded

Quote:
Originally Posted by Antoinel View Post
I have a great respect for Mr. Pass, you, and the rest of DIYers. Fortunately, I am not implying anything.

I clearly misunderstood the invention US 5,710,522, and thus misinterpreted the operation of the Aleph Current Source. %7#* happens said Arnold's Predator. My apologies to y'all for inadvertently causing negative emotions, frustration and other ill effects. But; my screwup has a silver lining and I am happy to report its upside:
  • The drive signals to the gates of the output JFETs in Conceptual F6 are out of phase like we've come to know and practice [e.g. by buzzforb, lhquam etc..]. This correct phasing is a fact, and is exactly like that in the invention US 5,710,522, and the Aleph Current Source. The upper output JFET in Conceptual F6 is a modulated current source load to the lower output JFET operating as the sole gain device. It follows from this analogy that Conceptual F6 is US 5,710,522; and in personal opinion, a simple and brilliant development.
  • The in-phase signal drive to the gates of the output JFETs in Conceptual F6 is not US 5,710,522 or the Aleph Current Source. There is absolutely no relationship or connection between US 5,710,522 and the in-phase signal drives to the gates of the output JFETs in Conceptual F6. But; is there a reason which will prevent you and/or I from driving the gates of the output JFETs in Conceptual F6 with in-phase signals? Absolutely not. buzzforb: thank you for your ongoing coaching to stop speculating and test instead my hypotheses by actual diy building. I will gladly do this experiment and report my findings in a couple of days. But, buzzforb, lhquam and others may wish to race me to the answer!
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Old 1st October 2012, 11:07 PM   #2186
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Your crazy!
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Old 1st October 2012, 11:15 PM   #2187
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Quote:
Originally Posted by Antoinel View Post
I clearly misunderstood the invention US 5,710,522, and thus misinterpreted the operation of the Aleph Current Source. %7#* happens said Arnold's Predator. My apologies to y'all for inadvertently causing negative emotions, frustration and other ill effects. .......

no negative emotions , I was just somewhat tired showing you that you're splittin' wrong hair


Quote:
Originally Posted by Antoinel View Post
.....[*]The drive signals to the gates of the output JFETs in Conceptual F6 are out of phase like we've come to know and practice [e.g. by buzzforb, lhquam etc..]. This correct phasing is a fact, and is exactly like that in the invention US 5,710,522, and the Aleph Current Source. The upper output JFET in Conceptual F6 is a modulated current source load to the lower output JFET operating as the sole gain device. It follows from this analogy that Conceptual F6 is US 5,710,522; and in personal opinion, a simple and brilliant development.
.........
well , if you insist on looking at upper Jfet as CS ;
that's one way of observing the reality (sez that man who sez - gimme support point and I would move the Earth) ;
but - contrary to Aleph CCS , F6's "CS" have no any connection with current going to load , which is ,naive me , pretty much important virtue of said Aleph CCS


Quote:
Originally Posted by Antoinel View Post
.......[*]The in-phase signal drive to the gates of the output JFETs in Conceptual F6 is not US 5,710,522 or the Aleph Current Source. There is absolutely no relationship or connection between US 5,710,522 and the in-phase signal drives to the gates of the output JFETs in Conceptual F6. But; is there a reason which will prevent you and/or I from driving the gates of the output JFETs in Conceptual F6 with in-phase signals? Absolutely not. buzzforb: thank you for your ongoing coaching to stop speculating and test instead my hypotheses by actual diy building. I will gladly do this experiment and report my findings in a couple of days. But, buzzforb, lhquam and others may wish to race me to the answer!
.......
some of possible variations are already shown here :
F6 Amplifier
but , without severe limitation of upper Jfet's modulation , you can hardly have any decent output ; and even then , efficiency of amplifier will be simply awful ; depending of said modulation limitation/attenuation , you'll have anything between total silencer and simple CCS loaded amp


so - we are here brainstorming about amp ; nothing more , nothing less
but , this isn't 42 chase

so - next time , contemplating about some theorem , please put some things in form of question , not fact ...... just because that way you're misleading ppl with lesser knowledge and experience

don't be afraid to be dumb ......... I'm exactly that at least 10 times/day

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Old 1st October 2012, 11:19 PM   #2188
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EWE! I forgot about number two.
Never mind. I am going for uber low distortion, then magic SE trick. All will have to wait for completion of M2 bastardo. Nothing like a good fight.
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Old 1st October 2012, 11:42 PM   #2189
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Quote:
Originally Posted by Zen Mod View Post
don't be afraid to be dumb ......... I'm exactly that at least 10 times/day

I am rarely afraid and afraid or shy to be dumb or stupid; This clearly showed already with my screwups. Fortunately this is a therapeutic hobby and not my core "science field" I depend on for bread and no trans-fat butter.
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Old 1st October 2012, 11:44 PM   #2190
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then buy any proper repeater and you can try even with pair of IRFP240 what's exactly happening
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