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Old 30th September 2012, 01:57 PM   #2121
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Quote:
Originally Posted by lhquam View Post
More Teaser-6 adjustments. I received two more SemiSouth R100s and measures their transconductance along with the two R100s from the channel that wasn't performing as well.

New R100 JFETS
Gm = 9.335S, 8.046S

R100 JFETS from suspect channel
Gm = 7.203S, 8.282S

I paired the 8.046S and 8.282S JFETs and reassembled the PC board.

I finally found the "sweet spot" for lowering 2nd harmonic in this channel. It appears to be somewhere near Rs = R05.

I am listening to it now and the sound is better than ever. With pots in parallel to the source resistors, it is easy to adjust for your preference of harmonic content and level of global feedback.

Here are the Harmonics vs Frequency sweeps for the two channels now.
As you can see, the 2nd harmonic is very low. The first plot is left channel that was previously the better one. The second plot is the newly configured and adjusted channel.

I still have no idea what harmonic balance and global feedback level Nelson is looking for.
lhquam has already matched the output JFETs to within 2.89% versus its original 13.9% which he called a poor performing channel. He clearly concludes to have converged on the sweet spot for Teaser-6. The new mismatch in transconductance [2.89%] still caused a DC offset at the output. This offset is a valuable number. It mirrors the intrinsic mismatch in the Gms of the JFETs. Its value is an objective guide to the extent of mismatch. Measure this DC output offset as a functon of Idss at a fixed frequency. Tweaking the bias pots to zero the output offset does not induce a new magical match between the JFETs. Au contraire, it creates a new mismatch by forcing the Idss of one JFET to track the other where it shouldn't. IMHO, one needs to adjust the bias pots of both JFETs to get one identical value of bias voltage. Allow the DC output offset to settle where it naturally has to due to the intrinsic mismatch of the JFETs. Use an output capacitor to block DC , and carry on.
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Old 30th September 2012, 02:22 PM   #2122
lhquam is offline lhquam  United States
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With the transformer coupling, I cannot see any reason that the absolute level of the FET bias voltage Vgs matters at all. The transconductance is important in determining the relative modulation levels of the two output FETs, and thus H2.

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Originally Posted by Antoinel View Post
... IMHO, one needs to adjust the bias pots of both JFETs to get one identical value of bias voltage. Allow the DC output offset to settle where it naturally has to due to the intrinsic mismatch of the JFETs. Use an output capacitor to block DC , and carry on.
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Old 30th September 2012, 02:32 PM   #2123
flg is offline flg  United States
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Quote:
Originally Posted by Antoinel View Post
lhquam has already matched the output JFETs to within 2.89% versus its original 13.9% which he called a poor performing channel. He clearly concludes to have converged on the sweet spot for Teaser-6. The new mismatch in transconductance [2.89%] still caused a DC offset at the output....
The G-S Threshold voltage of each device also plays a role in the "intrinsic mismatch" of the circuit (offset).
Quote:
Originally Posted by Antoinel View Post
...Measure this DC output offset as a functon of Idss at a fixed frequency. Tweaking the bias pots to zero the output offset does not induce a new magical match between the JFETs....
Au contraire I can undestand your use of "Idss" but, to assciate it with frequency? It more than likely adjusts the output offset and matches Id, causing a very slight mismatch in the Bias Voltage of the 2 deivecs. The Vgsth voltage will likely not be equal and this will be necessary for 0 output offset. These are DC conditions.
AC wise the Vgsth and Id mismatch, even after offset adjustment, will likely have much less effect on distortion than the gain variations due to tranconductance mismatch IMHO
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Last edited by flg; 30th September 2012 at 02:35 PM.
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Old 30th September 2012, 02:33 PM   #2124
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lhquam, I was slower at the keyboard but, I beleive I agree
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Old 30th September 2012, 03:05 PM   #2125
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It would seem that well matched devices would lead to lower level of harmonics out of the gate, considering the symmetrical signal of the transformer, but all I would do is screw it all up with some distortion. Opinion again
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Old 30th September 2012, 03:17 PM   #2126
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ya'll remember advices for venerable JLH amp , and choosing output with higher beta to upper(?) position ?
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Old 30th September 2012, 03:47 PM   #2127
lhquam is offline lhquam  United States
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Can someone point me to some original discussion or schematic for the "Zen amount pot"? The only schematic I have found is this: L'Amp: A simple SIT Amp

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would you recommend a pot with a value about the input impedance of the output stage or ten times smaller.......
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Old 30th September 2012, 03:49 PM   #2128
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Nope. Only read PLH. Never looked at JLH thread
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Old 30th September 2012, 03:51 PM   #2129
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Quote:
Originally Posted by lhquam View Post
Can someone point me to some original discussion or schematic for the "Zen amount pot"? The only schematic I have found is this: L'Amp: A simple SIT Amp
That it. You know the theory. It is simply about your taste and harmonic distribution. Have you tried it with F5T balanced yet? P3 is basically same thing, but control/alteration is coming from FE.
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Old 30th September 2012, 03:56 PM   #2130
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Quote:
Originally Posted by lhquam View Post
Can someone point me to some original discussion or schematic for the "Zen amount pot"? The only schematic I have found is this: L'Amp: A simple SIT Amp
started from here : L'Amp: A simple SIT Amp , later developed to L'Amp: A simple SIT Amp
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