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Old 10th September 2012, 10:57 AM   #1601
lhquam is offline lhquam  United States
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One bias current sense resistor in addition to measuring Vout offset should be enough. I have seen absolutely no problems with bias instability for any values of Rs between 0R12 and 1R. I haven't yet tried Rs=0R0, but I expect it to be fine.

BTW: I just ran calculations for Z0 and DF with the source degeneration removed. Z0=0R335, Df=23.9.

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Originally Posted by Antoinel View Post
Neat. Flip side to your suggestion. Will it be possible to have only one current sensing resistor [for example 0.1 Ohms]; in series with the drain of the bottom JFET [drain to Out]; or in series with the drain of the upper JFET [drain to V+] ? The LEDs of the bias circuits have a negative temperature coefficient. Maybe glued to the heat sink to maintain a steady idle bias!

Last edited by lhquam; 10th September 2012 at 11:06 AM.
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Old 10th September 2012, 11:13 AM   #1602
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Originally Posted by lhquam View Post
One bias current sense resistor in addition to measuring Vout offset should be enough. I have seen absolutely no problems with bias instability for any values of Rs between 0R12 and 1R. I haven't yet tried Rs=0R0, but I expect it to be fine.

BTW: I just ran calculations for Z0 and DF with the source degeneration removed. Z0=0R335, Df=23.9.
How to do that calcs mate? - this has me stumped ...
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Old 10th September 2012, 11:19 AM   #1603
lhquam is offline lhquam  United States
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The calculation was done using LTSpice and measuring Vout with 8 ohm and 4 ohm loads. The calculation was shown in earlier posts by both me and ZM.

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How to do that calcs mate? - this has me stumped ...
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Old 10th September 2012, 11:24 AM   #1604
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IN biasing up my output, I had one pot vlue way off from other. THe trafo did a phenominal job of keeping the bias consistent and stable, even at the expense of robbing the other half's bias circuit to do it. Bias you amp up again and intentionally throw off one half. Watch what happens. Also, doesnt Rs still have a stablizing effect on the output even if it is not included in the degeneration?
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Old 10th September 2012, 11:32 AM   #1605
generg is offline generg  Germany
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Originally Posted by Melon Head View Post
Where is stefanoo?
Nelson loves Elna Silmic. He has stack of them in his B5

Elna Silmic love stopped partially in Pass Laboratories, in the SIT 2 and one also, there are Clarity Caps PWA (SITs) or Clarity Cap ESA (XP30) types. But of course there might be a special selection for Nelson and Wayne......

So triode_al might be right wishing no electrolyt in the crucial places....
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Old 10th September 2012, 11:33 AM   #1606
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Originally Posted by lhquam View Post
The calculation was done using LTSpice and measuring Vout with 8 ohm and 4 ohm loads. The calculation was shown in earlier posts by both me and ZM.
Ok gotcha - got the measurement part down. What was interesting was the calculating bit - ie how to estimate open n close loop output impedance from MOSFET characteristic stats n curves....
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Old 10th September 2012, 11:41 AM   #1607
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Elna Silmic love stopped partially in Pass Laboratories, in the SIT 2 and one also, there are Clarity Caps PWA (SITs) or Clarity Cap ESA (XP30) types. But of course there might be a special selection for Nelson and Wayne......

So triode_al might be right wishing no electrolyt in the crucial places....
Nelson is more than happy interchanging between either polypropylene or Elna Silmic. But if it is not a Silmic put in a PP cap
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Old 10th September 2012, 11:48 AM   #1608
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Quote:
Originally Posted by lhquam View Post
One bias current sense resistor in addition to measuring Vout offset should be enough. I have seen absolutely no problems with bias instability for any values of Rs between 0R12 and 1R. I haven't yet tried Rs=0R0, but I expect it to be fine.

BTW: I just ran calculations for Z0 and DF with the source degeneration removed. Z0=0R335, Df=23.9.
lhquam. Will you consider a closed loop gain of 2-3 to further lower Zo? Will the FE be able to handle input signals 6 Vrms or higher? In the limit, what will the value of Zo be at a closed loop gain =1; provided Teaser-6 doesn't oscillate. Gotta push the envelope! Generous input signal levels are available per the opening paragraph of Mr. Pass in his article of B1. Best gain structure one could have!

Last edited by Antoinel; 10th September 2012 at 11:53 AM.
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Old 10th September 2012, 11:52 AM   #1609
Zen Mod is offline Zen Mod  Serbia
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Quote:
Originally Posted by buzzforb View Post
IN biasing up my output, I had one pot vlue way off from other. THe trafo did a phenominal job of keeping the bias consistent and stable, even at the expense of robbing the other half's bias circuit to do it. Bias you amp up again and intentionally throw off one half. Watch what happens. Also, doesnt Rs still have a stablizing effect on the output even if it is not included in the degeneration?
ya sure in verity of your explanation

besides that , any impression of sound between two variations ?

I presume better , with Rs not included in modulation path
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Old 10th September 2012, 11:54 AM   #1610
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ya sure in verity of your explanation
Nope.
Just know i started to bias the thing up by adjusting lower half of circuit. Got way ahead of upper half. LED's started to dim and went out. Bias across both RS was same. Pulled the fets, tuned post to where both bias voltages were the same. popped the fets back in, turned up the variac, LED's back on and bias coming up slowly. this was seconf time this happened. Also did it on Lateral version.
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Last edited by buzzforb; 10th September 2012 at 11:59 AM.
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