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Old 23rd August 2012, 09:51 PM   #1061
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Quote:
Originally Posted by lhquam View Post
Here is an F6 design that is fully symmetric in the spirit of a circlotron. The output power supplies float relative to ground, but not relative to each other. The harmonic distortion is primarily 3rd order. It will accept either balanced or unbalanced inputs.

I have simulated it with LTSpice and it looks very good.

The power spectrum plot in for 1 watt output at 1kHz into 8 ohms.
The best solution for the input until now.
And what about the use of a circlotron input stage?
Then the p-ch jFET is dispensable and I can use other types for the N-channel like the follow:
http://www.toshiba.com/taec/componen...nc/53/6937.pdf
or even a Sziklai darlington (CFP) instead a single jFET (e. g. consisting of a BF245 and a 2N5401).
The disadvantage of a second power supply isn't an issue - so I think.

Last edited by tiefbassuebertr; 23rd August 2012 at 09:55 PM.
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Old 23rd August 2012, 10:04 PM   #1062
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This thread is absolutely fascinating !!!
I have to go back and re-read a large portion to see if I can get my head around it.
I do know that I became intrigued with the "transformer interstage" when I built my F4 headphone amp (posts around 3400 in F4 thread) and I am now hooked.
Have the transformers and R100s - now will have to look for a chassis
Thanks to everyone
Back to reading
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Old 23rd August 2012, 10:11 PM   #1063
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Quote:
Originally Posted by lhquam View Post
The only difference from a circlotron that I know about is the position of the power supply V1 relative to the output FET.
  • In my circuit, there is the clockwise loop: Rload - V1 - R4 - J3
  • In a circlotron the loop is: Rload - R4 - J3 - V1
All remains the same (except the bottom of the bias circuit remains attached to the bottom of R4).
An appropriate name for your circuit in post#1055 is: The L. H. Quam Circlotron. Clearly, the F6 Amplifier thread was, and continues to be a source of your inspiration.
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Old 23rd August 2012, 10:13 PM   #1064
lhquam is offline lhquam  United States
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Quote:
Originally Posted by lhquam View Post
Here is an F6 design that is fully symmetric in the spirit of a circlotron. The output power supplies float relative to ground, but not relative to each other. The harmonic distortion is primarily 3rd order. It will accept either balanced or unbalanced inputs.

I have simulated it with LTSpice and it looks very good.

The power spectrum plot in for 1 watt output at 1kHz into 8 ohms.
A note about post #1055. If the node Out- is grounded, then the circuit reverts to a non-floating version. Here is the difference in harmonic distortion floating vs. grounded PS, particurly the lowering of the 2nd harmonic:

Floating PS, 1kHz, 1 watt into 8 ohms closed-loop gain approx 5.3:

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 1.000e+03 2.034e+00 1.000e+00 -0.50 0.00
2 2.000e+03 1.651e-05 8.116e-06 -170.34 -169.84
3 3.000e+03 1.622e-04 7.974e-05 5.35 5.85
4 4.000e+03 8.365e-06 4.113e-06 179.94 180.44
5 5.000e+03 7.235e-06 3.557e-06 -179.05 -178.55
6 6.000e+03 5.574e-06 2.740e-06 -179.96 -179.46
7 7.000e+03 4.780e-06 2.350e-06 -179.99 -179.49
Total Harmonic Distortion: 0.008041%

Grounded PS:

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 1.000e+03 4.013e+00 1.000e+00 -0.48 0.00
2 2.000e+03 6.831e-04 1.702e-04 153.26 153.74
3 3.000e+03 5.623e-04 1.401e-04 16.21 16.69
4 4.000e+03 3.786e-05 9.435e-06 -80.85 -80.37
5 5.000e+03 3.080e-05 7.674e-06 -165.27 -164.79
6 6.000e+03 1.509e-05 3.761e-06 168.18 168.66
7 7.000e+03 1.023e-05 2.549e-06 177.28 177.76
Total Harmonic Distortion: 0.022085%

This is the best THD under the same conditions from my previous design which has grounded PS:
Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 1.000e+03 4.042e+00 1.000e+00 -0.12 0.00
2 2.000e+03 6.355e-04 1.572e-04 24.32 24.44
3 3.000e+03 5.170e-05 1.279e-05 27.04 27.16
4 4.000e+03 4.809e-05 1.190e-05 -179.51 -179.38
5 5.000e+03 3.709e-05 9.175e-06 179.91 180.04
6 6.000e+03 3.073e-05 7.602e-06 179.74 179.86
7 7.000e+03 2.631e-05 6.510e-06 179.79 179.91
Total Harmonic Distortion: 0.015877%
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Old 23rd August 2012, 11:07 PM   #1065
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Old 24th August 2012, 12:15 AM   #1066
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Quote:
Originally Posted by Nelson Pass View Post
I am making an allowance for dissipation ratings of the input Jfets. Their
bias figure is not degenerated, so with some devices the current can get
pretty high. Also, this design can be run at higher rail voltages, maybe too
high for those inputs.

perfecto.. Thank You ( )
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Old 24th August 2012, 12:24 AM   #1067
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Well, we are all trying to figure out Papa's P6 design. I must retract my "circlotron-like" design because it is not novel in any of its concepts.

My question is whether Papa has devised a way to get circlotron symmetry without floating power supplies.

The asymmetry with my design in post 941 F6 Amplifier is mostly due to the transformer inter-winding capacitances. The floating power-supply design balances the effects of those capacitances eliminating most of the 2nd harmonic.
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Old 24th August 2012, 01:00 AM   #1068
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Impressive, Ilquam. I am officially in over my head. Schematics like yours remind me i still have a lot to learn.
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Old 24th August 2012, 01:10 AM   #1069
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Hi all,

Based on the findings so far from the many valuable contributions on this thread, plus key hints from mr. pass (#1051, #1058), this is something that may be worth playing with for folks with some parts on the bench and impatient. The final one we see from NP may well be very different but with so few parts, it wont be hard to change things around and have some fun meantime.....

Some points:

a) Since the biasing network is ground referenced, I have moved it to be closer to the one done by Ilhquam, (but still R biased here - can use voltage reference I guess if desired). The bias resistor network is high impedance so as to avoid any unwanted AC feedback paths in the op stage. If you go for voltage ref bias (led, zener, tlc etc) I think you'd still want to use a relatively high r network around it (no R should give a path of less than 20K or so to the gate)

b) Input stage I just used 100% per the simplified schematic (apologies to NP for my hack job on the schematic). I built it with no resistors in the drains and it seemed to work fine, no heating of the jfets either. Supply rails for V2 I just connected to V1. At 24 V rails and Idss of 10mA or so, that would mean max of 240mW which is a bit high so have to watch the Idss of your part else drop the rails a few volts. Mine were 6.4mA or so.

c) OLG should be very high so think that CLG should be circa 30x or 30db. Rf can be adjusted to suit. I suggest don't increase Ra much unless the tx has a very high DC-resistance as that would increase the driving impedance on the primary.

This should be a pretty spiffy amp once it grows up and matures

I will be travelling this next week so no soldering iron time but will be the first thing I try when I get back. Cheers!
Attached Images
File Type: png Test-F6-Schema.png (55.4 KB, 321 views)

Last edited by kasey197; 24th August 2012 at 01:14 AM. Reason: ref NP posts, rewords
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Old 24th August 2012, 01:43 AM   #1070
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Why is the bias network changed vs the previous version I tried since we now needs caps ? Simple - if we use the previous scheme, the bias resistor network needs to be low impedance. Why ? because if we made the network using high value resistors, the open loop freq response suffers very dramatically as the fets gates have no low-impedance path to source to discharge. The effect is very dramatic if you try it. In the schematic shown above, the low impedance AC path to source is provided through the caps and through the secondaries. The low value of gate stopper is also in aid of the same objective..... just in case anyone was wondering
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