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Old 23rd August 2012, 02:15 AM   #1041
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Thanks FLG. I will be using an older ADC transformer, so i will be headed down a different road than others with the Jensen's.
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Old 23rd August 2012, 02:24 AM   #1042
flg is offline flg  United States
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I have a couple Lundahl LL7905 I want to play with in front of an F4 circuit. I could see it in an F6 also???
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Old 23rd August 2012, 05:21 AM   #1043
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on a completely different note - has anyone figured out yet why two voltage rails for output stage vs input stage ? It can't be something trivial given that they are shown as distinct in the simplified schematic. Any clues anyone ?

Mr. Pass, maybe throw us a bone or two ? )
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Old 23rd August 2012, 05:52 AM   #1044
lhquam is offline lhquam  United States
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Quote:
Originally Posted by kasey197 View Post
on a completely different note - has anyone figured out yet why two voltage rails for output stage vs input stage ? It can't be something trivial given that they are shown as distinct in the simplified schematic. Any clues anyone ?

Mr. Pass, maybe throw us a bone or two ? )
EXCELLENT QUESTION

My initial guess was that the input stage rails are reduced to limit power dissipation on the input JFETs. But, knowing the devious nature of our Papa guru, I am now thinking otherwise.

Could the 2 supplies be floating relative to one another in circlotron fashion? The transformer would facilitate that, but the feedback would be different than shown. Perhaps he devised a different way to make a truly symmetrical amplifier from N channel only JFETs that is not a circlotron.

That would mean that I have been on a wild goose chase with my design. Not a total loss, since I have learned a few things along the way.

Last edited by lhquam; 23rd August 2012 at 06:05 AM.
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Old 23rd August 2012, 06:03 AM   #1045
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Originally Posted by Antoinel View Post
triode_ al: I like [and hopefully others will appreciate] your schematic in post #1023 because:
  1. The bias to the upper MOSFET is referenced to the output and not to ground. Thus; this MOSFET will always operate Class A. By contrast, lhquam has the corresponding bias in his prototype referenced instead to ground.
  2. The bias to the upper MOSFET is [hopefully] stable due to the CCS you used to establish it. I would have used [on paper] an independent power supply of positive voltage higher than the rail voltage shown. Bias in this newer instance will be granite solid or better. By comparison, kasey197, uses a resistor voltage divider to establish bias in his prototype. It may suffice. But; it may also appear to be less robust [rock stable] than the one you are using.
  3. The bias to the bottom MOSFET can be anything else that is stable; which you do show, and others do.
  4. The blocking capacitors in series with the gates of the MOSFETs eliminate the dreaded direct current through the secondaries.
re
  1. The bias is like the conceptual scheme:
    F6 SIMP.gif
    It is attached to the output where the voltage across the xfrm is 0. A cap does the same in a different layout.
    Yes, I could use a bootstrap to the power supply of the CCS of the top circuit. Is a good idea. But that implies I use the same time constant in all 4 bias circuits (or else - I have huge bumps, worse than goose bumps ).
    CCS (near-contant current) is different from near-constant voltage like Kasey does, but the effect can be the same, only my bias is adjustable and I like to be able to set the current like in the F5 - to manage the output zero.
    I do have a separate PS for the input buffer, running at +/- 35V and that leaves enough headroom for the bias so I won't have troubles in minor shifts in the CCS.
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Old 23rd August 2012, 06:47 AM   #1046
lhquam is offline lhquam  United States
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Default Floating V1 supply concept

Quote:
Originally Posted by kasey197 View Post
on a completely different note - has anyone figured out yet why two voltage rails for output stage vs input stage ? It can't be something trivial given that they are shown as distinct in the simplified schematic. Any clues anyone ?

Mr. Pass, maybe throw us a bone or two ? )
Here is an idea of the circlotron-like amplifier. Feedback uses the 4th transformer coil.

Note that if you move V2 to between J2 and Out+ you have a circlotron.
Attached Images
File Type: jpg F6B-concept.jpg (49.3 KB, 389 views)

Last edited by lhquam; 23rd August 2012 at 06:55 AM.
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Old 23rd August 2012, 08:56 AM   #1047
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Originally Posted by buzzforb View Post
In trying to determine the ideal load resistor for the transformer, does the circuit need to be complete including output stage or can it be determined with just the transformer connected to the input stage?


complete

tell me which sch you are going to use , and I'll tell you what part you need to vary
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Old 23rd August 2012, 09:34 AM   #1048
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Originally Posted by Zen Mod View Post
complete

tell me which sch you are going to use , and I'll tell you what part you need to vary
I am going to try multiple, but had intended to start with b1 bias schema. Ill draw it up like i got it wired. Hopefully it wont blow up. Just to be stubborn, i am going to trywith secondaries wired in phase. The SILENCER sounds really cool, and i need to learn anyway.
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Old 23rd August 2012, 04:00 PM   #1049
lhquam is offline lhquam  United States
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Quote:
Originally Posted by lhquam View Post
Here is an idea of the circlotron-like amplifier. Feedback uses the 4th transformer coil.

Note that if you move V2 to between J2 and Out+ you have a circlotron.
I did a Spice simulation of this idea but the high frequency response was bad. The response is down 3dB at about 10kHz. I tried a variety of different impedances for the feedback network.
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Old 23rd August 2012, 05:44 PM   #1050
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Originally Posted by lhquam View Post
I did a Spice simulation of this idea but the high frequency response was bad. The response is down 3dB at about 10kHz. I tried a variety of different impedances for the feedback network.
Why burden your circuit with negative feedback? Without NFB, the output stage is Circlotronic, has high power [value?], and low distortion [value?]. What else are you seeking? Most probably you'll say a low output impedance; but where will its physical location be ? Will the low output impedance be at the junction of the power supplies and/or the joint between the source of upper JFET and the drain of lower JFET. Your thoughts!
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