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Old 31st March 2012, 07:38 PM   #1
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Question Semisouth SiC gate protection?

Finally I got some SiC power JFETs. They are quite expensie, so I would not like to damage them.

How do you protect the gate? Do you use Zeners? What is the safe value of gate stopper?

Anatoliy
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Old 31st March 2012, 07:51 PM   #2
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what is SiC power JFETs .
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Old 31st March 2012, 07:53 PM   #3
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Mine are SJEP120R100A
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Old 31st March 2012, 10:39 PM   #4
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Mine too. I use 13V zener for protection and 100 Ohm gate stoppers. Thx. to ZenMod!
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Old 1st April 2012, 02:09 AM   #5
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Quote:
Originally Posted by Nelson Bass View Post
Mine too. I use 13V zener for protection and 100 Ohm gate stoppers. Thx. to ZenMod!
Thenks to you both!

But does not Zener limit positive voltage, or you use bi-directional one?
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Old 1st April 2012, 03:00 AM   #6
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Quote:
Originally Posted by biju55 View Post
what is SiC power JFETs .
fully sic power devices
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Old 1st April 2012, 06:25 AM   #7
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positive is enough

same as you want to protect 6H23П

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Old 1st April 2012, 08:17 AM   #8
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Quote:
Originally Posted by Zen Mod View Post
positive is enough

same as you want to protect 6H23П

Let's pretend it's March 32 today, ok?

According to datasheet it wants positive voltage on gate, it is in cut-off at zero volt. That means we need to protect it from too high negative voltage, against positive voltage it's own p-n junction protects itself.
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Old 1st April 2012, 09:25 AM   #9
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whatever you say , on March 32.

same as with mighty n32p , when dc connected to some drek in front ....... you need to protect it from excessive positive voltage on gate .

though , even if I didn't had negative experience , my friend scorched few of them , due to few mistakes and wrong parts in preceding circuit
for these , I'm pretty sure that positive peak kill them

I don't have experience in vivo for negative ........... and I also think that you don't need any protection in finished construction , when tests are over
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Old 1st April 2012, 02:30 PM   #10
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The d/s for this 100A part provides plenty of info about G-S SOA. Let's see.
First, we see max Vgs for AC is -10...+15V. For the test conditions specified
(Rg ext. of 1Ω and T≤200ns) that makes forward conduction short pulses of approx. 13A through the gate
Then, in the next table we see Igss specified, as DC, for -10V gs.
Next, on Fig. 5 for DC operation, Ig can be easily allowed to be ≥1A.
On Fig. 8 we see, that gate current can be ~1A to achieve "improvement"
(ha-ha) from 92mΩ to 78mΩ Rdon.
So, clearly, staying well within -10V Vgs limit, and making sure, that
forward Ig current will be well below 1A, this part should perform very well. The rest is just ordinary engineering (I mean, not to test your luck).
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