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Old 9th December 2012, 10:02 AM   #231
NicMac is offline NicMac  Italy
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>As with all properly designed protection circuits, the passive state (no power) is the safe state. i.e. muted.

That was what I reasoned.

>However if you also volunteer to test, and soon, contact WK to arrange a set of mechanical hardware to be sent to you. Best to contact him by email.

WK has e-mail. I should have the time in January/February to test.

No comments on my front-end bias? Just curious.

Cheers,

Nic
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Old 9th December 2012, 04:01 PM   #232
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What are the Idss of your JFETs ?


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Old 9th December 2012, 04:21 PM   #233
heinz1 is offline heinz1  Europe
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Two minor errors/additions in the BOM:

- R45, R46 (Susumu 0805 SMD, 5.1 R): The BOM claims four of these per channel, but in the schematics and on the board, there are only two.

I assume these two would go to the two small, unlabeled and asymmetrically located SMD pads on the back of the board near the JFETs/cascode elements. Correct?

- You might want to add the "-Y"-suffix to the "MFG PN" column for the power MOSFETs.
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Old 9th December 2012, 04:40 PM   #234
NicMac is offline NicMac  Italy
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>What are the Idss of your JFETs ?

About 7.9 mA
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Old 9th December 2012, 06:11 PM   #235
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Then I expect you to get 6~7mA bias rather than 4.4mA.
You could have checked by just measuring the Id of each JFET with 10R degen.
That should be roughly your bias for the fist stage.


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Old 9th December 2012, 07:10 PM   #236
NicMac is offline NicMac  Italy
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> You could have checked by just measuring the Id of each JFET with 10R degen.

I could indeed have, especially if I knew that I ought to.
Is there a "sweet-spot" to aim for?
Should I just leave it or would I be better of fixing the problem in some way?
I guess I could easily lower the 11R triplets with some parallel (matched) resistance (mounted on the underside of the PCB), but I'm not sure if this is the way to go.

Anybody else measured these currents?
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Old 9th December 2012, 07:59 PM   #237
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Hi Nick,

Quote:
Originally Posted by NicMac View Post
>What are the Idss of your JFETs ?

About 7.9 mA
Quote:
Originally Posted by NicMac View Post
> You could have checked by just measuring the Id of each JFET with 10R degen.

I could indeed have, especially if I knew that I ought to.
Is there a "sweet-spot" to aim for?
Should I just leave it or would I be better of fixing the problem in some way?
I guess I could easily lower the 11R triplets with some parallel (matched) resistance (mounted on the underside of the PCB), but I'm not sure if this is the way to go.

Anybody else measured these currents?
The Idss of the sets I put together came in at 6.8mA for the K170s and 7.8mA for the J74s. The front end current measured for these is ~4.8mA in circuit. See the chart here for ballpark targets for Idss and Rdegen based on calculations from the datasheets.

If your J74s and K170s in each set are the same Idss I don't think you will want to use the 5R1 degen resistor that is mounted on the bottom of the amp board. Substitute a zero ohm or small wire there. This resistor serves to more closely match the gain curves of the J74s to that of the K170s but only when the J74s are selected with higher Idss as described in the post/chart linked above.

Dave
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Old 9th December 2012, 08:17 PM   #238
NicMac is offline NicMac  Italy
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My 7.9 mA device Idss is for both the K170, and the J74 (after degeneration with appropriate Rdeg).
You get 4.8 mA front-end bias with 6.8 mA device Idss, while I get 4.4 mA with 7.9 mA device Idss. Any explanations come to mind
Anyway, maybe my 4.4 mA front-end bias is just fine.... I just don't know what to go for.
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Old 9th December 2012, 08:56 PM   #239
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Quote:
Originally Posted by NicMac View Post
My 7.9 mA device Idss is for both the K170, and the J74 (after degeneration with appropriate Rdeg).
You get 4.8 mA front-end bias with 6.8 mA device Idss, while I get 4.4 mA with 7.9 mA device Idss. Any explanations come to mind
Anyway, maybe my 4.4 mA front-end bias is just fine.... I just don't know what to go for.
Inputs to the AMP/JFETs grounded? Otherwise I don't know. Best match for me was using 4R for degen - so my JFETs were lower than datasheet typical numbers for gain. What are you using for Rdegen and do all four corners measure the same bias current?

Dave
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Old 9th December 2012, 09:11 PM   #240
NicMac is offline NicMac  Italy
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Inputs are grounded. I'm using four different Rdeg's for the four J74's
These are the measured values (mV drop over the 11R blocks) of the eight corners:

L: 48.1, 49.1, 47.8, 49.8
R: 48.1, 49.2, 48.0, 49.0
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