F5X -- the EUVL Approach - The Build Thread

[EUVL]

I have done the layout.
You will get 4x new PCB.

Shall let you know when ready.


Patrick

[Nikon1975]

I think I found few minor mistakes in the BOM:

1) Lines of R14A, etc. and R14B, etc. are inverted.
2) Optional protection circuit:first line, I thin it's not R9, but R4.

D.

[EUVL]

Thanks for reporting.
Dave will check and rectify.


Patrick

[Nikon1975]

Please check also the line of the alternative Caddock source resistors. I thin one or the resistors number is not correct.


But I wanted to ask you another question: I am selecting the JFets. In the BOM 6.6 and 7.2 Idss are indicated, but this does not match with the formula you posted in the F5 thread. Or you are using a different value for Yfs.

Additionally, how close should the match be? It's not so easy to find BL at that Idss, we may want to look on GR with high Idss.

D.


Quoting:
Idss (2SJ74) = Id * (1 + Rs*Yfs)
where Id = Idss of the 2SK170 in this case; Rs =5.1R; Yfs = 0.033 S for 2SJ74 at that bias range

Some sample calculations:
2SK170=7mA
6mA(1+5.1*0.033)=6.0mA(1.1683)=7.01mA for 2SJ74
6.5mA(1+5.1*0.033)=6.5mA(1.1683)=7.59mA for 2SJ74

[EUVL]

I have mailed Dave about the mistakes but he has not read my mail yet.

> In the BOM 6.6 and 7.2 Idss are indicated, but this does not match with the formula you posted in the F5 thread.

The formula is an approximation assuming Yfs is constant.
But Yfs varies both with Idss and actual Id.
You can put in the entire full JFET model equation to calculate if you wish to be more exact.

> Or you are using a different value for Yfs.

These are also only typical figures. Real FETs have different values.

> Additionally, how close should the match be?

I have also published a table listing various values of Idss for both FETs.
The easiest way to match, if you have many JFETs, is to actually use a 5R1 degen resistor, gate to Gnd and measured degenerated Id for the J74s.

How well match depends on how much even harmonic cancellation you want between top and bottom halves.
It also depends on how well match the MOSFETs Vgs at 2A are.
In practice you want as good cancellation as you can get from top to bottom, and let the left / right take care of what is left.
This is the advantage of the balanced F5 and has been discussed multiple times in more detail elsewhere.

It is much easier to get left-right match then N-P match.
So don't go too extreme on this.


Patrick

[EUVL]

Dave has actually done some measurement on this (J74 Idss for degen) and it should be in part 2 of his build article.
I have already seen the draft, so it should be up soon.


Patrick

[Nikon1975]

In the latest schematic of the F5, I think our R12, R13, R30, R31 was 22k, instead of 10k. Did we do any thought on this ? I know, it's a minor thing.

:-)

D.

[Nikon1975]

Originally Posted by EUVL

The easiest way to match, if you have many JFETs, is to actually use a 5R1 degen resistor, gate to Gnd and measured degenerated Id for the J74s.

So, in the actual test measurement would be R5.1 connected between S and G.

G connected to +16V
D connected to GND

measuring the current flowing in the drain.

Correct ?

D.

[EUVL]

> In the latest schematic of the F5, I think our R12, R13, R30, R31 was 22k, instead of 10k.

It is because the standard F5 use 24V rails instead of 16V.
You can go to the original NP article on F5 to dig out the maths how to calculate this.
My original protos has 10k, so I stick to that.

> Did we do any thought on this ?

Of course. Nothing are left to chances.

> I know, it's a minor thing.

We try to be correct, as many people are copying, and consequences of mistakes are costly, for you and for us.


Patrick

[EUVL]

How to measure J74 has already been described in the 3-point match document.
But here is it again :

PSU 0V to -13V (or -16V, does not matter so much). Important is negative supply for P-FETs.
Gate of J74 connected to 0V (via an optional 100R resistor).
5R1 connected between 0V and J74 source.
J74 Drain connected to -Vs.

Measure current Id.

If still not clear then post a schematics and I shall let you know if correct.


Patrick