F5 Turbo Builders Thread

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This also an exercise for me to learn and for fun vs. a definitive answer. I welcome corrections / additions.

2 N and 2 P boards per channel...

0V370 (if you had 0.370mV, that'd be pretty pitiful) ;) across 0R5 (I think the test points measure the equivalent of the points across both source resistors in parallel for each output device. So, 0A740 per vertical set. 4 Vertical sets per "phase". 4 Ns and 4 Ps. => ~3A => 6A of "Class A current" before we go klunk with push/pull.

Rails +- 48 less ~4Vish in loss => +- 44V => running balanced / differential => 88Vp => 176Vpp => ~62Vrms before voltage clipping.

Into 8R you're going to go klunk before you hit the rails.

6A gets you to ~290W into 8R

I screw this up ALL the time.... so, someone will likely be along momentarily to fix my errors. BUT... that does seem to agree pretty well with the article... So, I've got that goin' for me... which is nice.

Edited to fix some silly autocorrect... LOL!
 
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Rule of thumb is that each pair of BL JFETs are sufficient for 2 or 3 pair output. More than that is better served with more devices.

As you add more input (or output) devices in parallel, the open loop gain drops a bit because the drain resistance has to become smaller for the same Vgs, and more pairs also require less Vgs. The gain of the first stage is approximately drain resistance divided by source resistance. This is slightly offset by the increased transconductance of the (bigger) output stage.

Best to put it on a sim, but if you have no problems with 4 pairs and a single input pair, you should stick with it.