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Old 8th March 2013, 06:55 PM   #1521
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Smarty Pants.
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Old 8th March 2013, 10:50 PM   #1522
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Guys, in the first post in this thread ungie wanted to build F5T with FQA36P15 P Channel QFET and FQA28N15 N Channel QFET. I lost track in the thread, has it been discussed how do these sound and what BIAS, R7/R8 they need and how many W can they produce in comparison with IFP240/9240?
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Old 9th March 2013, 07:02 PM   #1523
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Default Bias going up automatically

I am building F5T turbo v2 version.

After a number of turns on the pots I got the Bias to 260 mv with dc offset of 20mv. I let it cook for some time may be half hour I see bias at 310 mv. then I switched it off. Is there some thing wrong here.

Is it common for bias to go up some millivolts. If so by how much would be limit.

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Old 9th March 2013, 07:05 PM   #1524
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Yes. Heat makes them conduct more. That is why Nelson advises letting it get good and warm before final bias. If wanting to go higher in bias, you must repeat procedure, as it will drift up again with increasing temp.
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Old 9th March 2013, 09:45 PM   #1525
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I was thinking and looking into leaving class A article... You bias transistors more to stay in class A longer, so your bias determines output current in class A. My question is what about minimum bias per device if you have multiple ones? Can you go up in number of outputs lowering bias per device but having the same(or even higher) total value? Is there a best spot? Or you can increase number of outputs until their capacitance kicks in and increase HF distortions?
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Old 9th March 2013, 09:53 PM   #1526
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This question has been asked of Nelson. One major advantage of bias spread over a number of devices is that the ibdividual fets iperate at a lower internal temp even though the cumulative heat may be higher. It would seem to allow for much greater safety margin in overall sink tempetature. Also, multipke parallel fets sum to higher overall YFS, which i believe, reduces somewhat, the effect of Crs, as less current is needed. Seems like a good idea, to me.
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Old 9th March 2013, 09:54 PM   #1527
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Read the F5T article, after the V3 section - Nelson adresses the paralleling question.

But for bias, he likes them working hard.
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Old 9th March 2013, 10:01 PM   #1528
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Thanks guys! I will check F5T paper, shame on me I missed it :-).

Buzz, you know why I am asking, right? ;-) some theoretical knowledge before brute experiment will put everything in place :-)
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Old 9th March 2013, 11:54 PM   #1529
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As I am learning and trying to understand the last 4 post, so feel free to correct me if I am wrong. But biasing the outputs lower across more outputs, would you then be reducing current across the fets reducing operating tempature, thus not needing as much heat sink. This might be exactly what buzz said, but I have to explain back to make sure I fully understand.
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Old 10th March 2013, 12:07 AM   #1530
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Almost. Each fet will operate at a lower individual temperature, but the total dissipation may be the same, epending on your choices. In other words, V2 biased @ 1A/fet vs V3 biased @ .5A/fet. Total dissipation is the same, but each fet is contributing less to that total and in theory has a little more safety margin as well as longer life. Also wonder about memory distortion, but that is VooDoo.
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