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Old 17th February 2012, 04:33 PM   #131
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Join Date: Jan 2010
Location: Harrow, UK
From the F5 manual.

"Initial Adjustment
Before applying power to the amplifier, you will want to set the values of P1 (TP3&TP4) and P2 (TP5&TP6) to their
minimum. Verify this with an ohmmeter. When it comes times to “fire” up the amp first time,
if you have a Variac, use it, fusing the AC line to the amplifier with a 1A fast blow fuse. Turn
the Variac up slowly, and if you haven’t popped the fuse, then go ahead and confirm the rail
voltages to the channels (TP1& TP2).
Each channel does not need to be attached to a load in order to adjust it. If the only load
you have is the loudspeaker, I would advise against using it during adjustment. For each
channel you will be adjusting P1 and P2 alternately in order to achieve 0 volts DC at the
output (TP7) and .59 volts across R11 (TP8&TP9) and R12 (TP10&TP11). Each time you adjust P1 you will probably have
to go back and adjust P2 again, and so I recommend adjusting the pots in half-measures,
alternately setting the pots half-way to their voltage goals and measuring the DC values.
Unless there is something very wrong, when the output is at 0 V DC, the values across R11
and R12 will be equal.
In spite of the thermal compensation in the circuit, you should assume that there will be drift
as the heat sink temperature rises, and you will need to readjust the values over the course
of an hour or two. Usually it is best to start out bias adjustment low, at maybe 0.4 mV
across R11 and R12 until the amp is warmed up a bit.
You should be able to get the output DC offset down to 10 mV or so, and I would consider
50 mV the highest acceptable figure for this amplifier when warmed up. After the amplifier
has been operated for a few weeks, it is a good idea to check and adjust the offset again
after the parts have been burned in."

TP10 & TP5 are indeed connected to the same track. I proved the two point to make it obvious which test was being carried out. You don't have to use them if you don't want to (same with TP3 & TP9).

I could add a track to the bottom but it would be narrower than the top track to maintain track to pad and track to track spacing. However, as the tracks to the source are 3mm wide and the board will be 2oz copper not 1oz I thought it unneccesary.

Andy
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Old 17th February 2012, 04:33 PM   #132
sangram is offline sangram  India
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Quote:
Originally Posted by UKToecutter View Post
(I could put some mounting holes if people would like them).
Yes please. We have some heavy TO-247 devices on the opposite end, and some high-current PSU wire. There's enough metal at both ends to make me want some support - even though it can be achieved with the board resting on a standoff in the non-coppered areas, a hole or two per side wouldn't be hated.
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Old 17th February 2012, 04:37 PM   #133
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Quote:
Originally Posted by bobodioulasso View Post
Input transistors including cascodes are very close to high output currents.
Might be an issue?
Yes, seems to be.
I've moved them closer to the JFETs
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Old 17th February 2012, 04:49 PM   #134
skunark is offline skunark  United States
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Has anyone reviewed the universal mounting spec for this board? I would be grateful if the F5 v2/3 boards could abide by it.
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Old 17th February 2012, 04:54 PM   #135
lhquam is offline lhquam  United States
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I now understand the problem: the source resistor designations have changed from the F5-Manual to the F5-Turbo-V3 schematic. Your layout has test points across R11 and R12, for bias adjustments, which were the correct resistor designations for the F5, but not the F5-Turbo. You need to measure bias voltages across R17 (or R18, r19, R20 ...) and R21 (or R22, R23, R24, ...).

Quote:
Originally Posted by UKToecutter View Post
From the F5 manual.

"Initial Adjustment
...

For each channel you will be adjusting P1 and P2 alternately in order to achieve 0 volts DC at the
output (TP7) and .59 volts across R11 (TP8&TP9) and R12 (TP10&TP11). Each time you adjust P1 you will probably have
to go back and adjust P2 again, and so I recommend adjusting the pots in half-measures,

...

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Old 17th February 2012, 04:55 PM   #136
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Quote:
Originally Posted by skunark View Post
Has anyone reviewed the universal mounting spec for this board? I would be grateful if the F5 v2/3 boards could abide by it.
Skunark

It can't be followed for this board.
The UMS has a 40mm pitch between the MOSFETs. That would make this board too large for the heatsinks that are proposed.
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Old 17th February 2012, 04:57 PM   #137
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Quote:
Originally Posted by lhquam View Post
I now understand the problem: the source resistor designations have changed from the F5-Manual to the F5-Turbo-V3 schematic. Your layout has test points across R11 and R12, for bias adjustments, which were the correct resistor designations for the F5, but not the F5-Turbo. You need to measure bias voltages across R17 (or R18, r19, R20 ...) and R21 (or R22, R23, R24, ...).


[/LEFT]
[/FONT]...
Oh bugger,

Thats a faux pas from me.
I assumed he'd kept the same resource designators.

Humbled and embaressed.

I'll correct that now.

Sorry
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Old 17th February 2012, 05:04 PM   #138
lhquam is offline lhquam  United States
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Quote:
Originally Posted by UKToecutter View Post
Skunark

It can't be followed for this board.
The UMS has a 40mm pitch between the MOSFETs. That would make this board too large for the heatsinks that are proposed.

How about when only 2 MOSFETS per rail are used, such as Q9, Q3, Q5 and Q11? Can the UMS spacing be made work for that situation?
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Old 17th February 2012, 05:08 PM   #139
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Quote:
Originally Posted by lhquam View Post
How about when only 2 MOSFETS per rail are used, such as Q9, Q3, Q5 and Q11? Can the UMS spacing be made work for that situation?
Probably, but that would mean a seperate v2 and v3 board
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Old 17th February 2012, 05:18 PM   #140
lhquam is offline lhquam  United States
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Quote:
Originally Posted by UKToecutter View Post
Probably, but that would mean a seperate v2 and v3 board
BTW: You should change the designation on your layout to:

"F5 Turbo v3" rather than "F5 Turbo v2".
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