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Old 14th July 2011, 10:32 AM   #21
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Wrenchone or Nelson or anybody,
Would you mind explaining gate leakage and the problems it causes? Haven't been able to find any real specific info on the net.
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Old 14th July 2011, 12:35 PM   #22
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Gate leakage in a MOSFET is caused by impurities or holes in the Gate Oxide. Between the gate and the channel (Source and Drain) there is an oxide layer grown to a specific thickness. The thickness determines the maximum gate-source voltage. The oxide is a dielectric, no current should flow thru it and it should act like a capacitor to the Source and Drain.
However, they leak? If you don't help the gate stay at the voltage you want it at, the leakage will allow a voltage to develope at the gate. A MOSFET gate left floating will likely float up and turn itself on. A pulldown resistor of some type is always a good idea. It can be very large ussually because there is very little leakage in MOSFETs.
SiC and JFETs??? The level of leakage we are starting to here about in these SiC devices suggests that the pulldown (ussually our input load setting value, maybe 47k) needs to be much smaller or the input leakage will create it's own unexpected bias to the device. Turn it on, off, whatever. If you don't design in for that current to your circuit, you might be suprised. In fact, these currents seem so unussually high, you might need a stronger driver circuit to drive the input resistors to circuits with SiC leakage
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Old 14th July 2011, 01:04 PM   #23
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Thanks FLG. Is this why Nelson doubled up the 109's on the FE of the J2? Doing so also reduces the resistor size for the bias voltage and lowers source resistance, all adding up to the FE having an easier time driving the SiC devices, correct? More current and less resistance. Also, he talks of a large cap that he has used. Other than for coupling the input, does this help with the gate leakage?

Last edited by buzzforb; 14th July 2011 at 01:08 PM.
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Old 14th July 2011, 01:31 PM   #24
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I think the reason N.P. doubled up on the Inputs of the J2 is that the bias voltage needed at the gate of the SiC device is low. Maybe 1.5Vgs vs 4.5Vgs with a MOSFET. This neccesitates a smaller drain resistor from the input circuit or lower current thru the input circuit. This will likely reduce the gain of the input circuit. So, he reduces the drain R of the input circuit to 220 ohm or so and uses two devices to recoupe the lost gain.
I don't know about the large cap? Where?
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Old 14th July 2011, 01:50 PM   #25
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Quote:
Originally Posted by flg View Post
I don't know about the large cap? Where?
The input cap on the amp at the beginning of this thread.

Sorry if this is threadjack, Wrenchone, just trying to understand what you are talking about as I have some of these same parts.
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Old 14th July 2011, 02:06 PM   #26
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O.K. right. With the smaller Rs at the input, the input cap will be creating a highpass filter. It will have it's f3 raised by smaller Rs unless you use a bigger Cap.
I don't think we're thread jacking, we're talking about his circuit and his discoveries. What we don't know is what we are talking about? Where's the schematic??? Stop trying to be "the one and only" feeding us bread crumbs or something and show us this cupcake?
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Old 14th July 2011, 03:23 PM   #27
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How do you measure leakage as i am soon to start on a SiC amp.
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Old 14th July 2011, 04:52 PM   #28
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The Data Sheet for the R100 SS parts seems to indicate a 0V D-S and a MaxBVds D-S with the Gate at -max G-S and measure gate current. That is: Drain gnd'ed and source Gnd'ed, with the gate at -15V measure gate current. And D@ 1200V and Source Gnd'ed and measure Gate current. (put a large enough resister in the gate line to measure 100uA or whatever)
This is another unreasonable test for us linear operating ClassA nuts? We should put something like 0 to +2.5V on the gate and 2-50V D-S and measure gate current. Like our operating conditions.


Except for Wrenchone: He needs to use 320Vds or whatever and what did he say for the 085 -9Vg-s. Might be more difficult for his SS glass idea with 085?
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Old 14th July 2011, 05:12 PM   #29
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THanks FLG.
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Old 14th July 2011, 05:34 PM   #30
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The reason I doubled up the JFETs on the input of the J2 was not associated
with Gate leakage. In fact, Gate current goes the other way in the
enhancement mode parts since the PN junction is forward biased.

We are talking about Gate current seen in depletion mode, and as I said this
is anywhere from 1 uA to more than 100 uA. If you are biasing the Gate
through a 47K resistor, you will have to allow for that voltage drop. Your
choice (besides going back to Mosfets) is to select for low leakage, lower the
DC source impedance, or provide a tracking mechanism.

This is not unique to the SemiSouth parts - Gate leakage is seen with other
JFET and SIT/Vfet parts.

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