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Old 26th May 2012, 03:36 PM   #191
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If you want to stay with just 2 tr. SRPP, then you can add local volt FB
to reduce output imp.
See attach.
This shunt VFB will also reduce input imp - R5 need to be of several KΩ.
R6 will set the gain - make it tens KΩ.
R4 will set the output volt center/midpoint, like +25V. Pot in megaohms range (or two resistors in series).
C1 needs to be as high as possible, 10F or more, and of a good quality.
R3 like 30-50 KΩ.
With Q1 being SJEP, R2 value can be selected by listening. You can start
with zero and progress towards ~0.4 Ω. It will affect distortions, speaker damping, gain.
Without speaker, this circuit will need equivalent resistor of speaker Ohms value for bias to function properly.
Your Fairchilds do not belong in SRPP.
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File Type: jpg Depl. SS SRPP.JPG (16.7 KB, 184 views)
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Old 26th May 2012, 03:51 PM   #192
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Interesting. Unfortunately I do not have SJEP, that is why I was working with SJDP. If using enhancement mode device on bottom, LTP becomes overly attractive for what it adds. I guess it reasonable to think that non LTP input may sound better since a gain stage is dropped. Only testing will tell. Is R4 sets bias, but is it also functioning as Schade feedback? Could throw this together with FQA on bottom or maybe even lateral 2sk. THey are the only enhancement devices I have. THanks. THis gives me something to study and build. ZM pointed me to some good reading. I will be playing with this for a while I think.
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Old 27th May 2012, 11:19 AM   #193
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Will this work? Lm317 based voltage regultor for higher current than other wise possible with just regulator. MAy have to parallel the fets as this psu could see up to 4-5A at 35-35V. Just trying to use what I have on hand. It is not for scehmatic above and does not include gate stopper or protection diode. THought it might need a resitor in front of lm317 for current protection, but unsure.
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Old 27th May 2012, 02:26 PM   #194
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LM317 Datasheet, Circuit Schematic, Pinouts and Sources
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Old 27th May 2012, 03:06 PM   #195
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How about this
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Old 27th May 2012, 03:20 PM   #196
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better

btw. - funny way for drawing diode symbol

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Old 27th May 2012, 03:26 PM   #197
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Been using crappy Express PCB software too long. Rarely use the schemtic editor, just pcb drawing tool. Do I need zeners to protect gates?Ant other improvement suggestions. I figuring this will max out at about 4A. May change the fet resistosr to parallel .47R for more current capability. Any improvements possible or is ths decent.
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Old 27th May 2012, 03:35 PM   #198
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zenner protect can't harm

for what you need that ?

see Papa's regs in Zen series

ZV3 , ZV4
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Old 27th May 2012, 03:42 PM   #199
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Diy curve tracer psu. Need 36V+ and about 5A of clean power. I could do big clc, but didnt know if that was adequate as i think the needs for big Class A power amp are not as great in comparison to digital baseed stuff.
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Old 27th May 2012, 03:53 PM   #200
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And if you have to stay with SJDP only, you just combine the two sketches
I have posted into one attached.
The new negative voltage reference will set both JFets to the selected current bias, pot in the voltage divider will set the output node to the ~half of the supply voltage. Just find the lowest value for R2, that will work for
your speakers and your ears (again, it's a balancing act). Here R4 will be tens KOhm.
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