This is a cooling issue. Let's imagine that you do a good
job of cooling the LU1014's. From there it's an easy jump
to more power. You will increase the current through the
Jfet and at the same time you will increase the Vds.
This gets you the current you need, and the increased Vds
lowers the capacitance of the part in addition to supporting
the higher current with more transconductance. Probably
you will want to reduce the Source resistance in the
process, but I have not determined the specifics.
Having done that, you can safely parallel the cascode
devices, giving each some Source resistance and matching
to ensure sharing, and you will also parallel the current
source transistors on the top, also adjusting their gain
networks appropriately.
The result will be lower distortion and more speed, which
you will need to support higher power.
This is a cooling issue. Let's imagine that you do a good
job of cooling the LU1014's. From there it's an easy jump
to more power. You will increase the current through the
Jfet and at the same time you will increase the Vds.
This gets you the current you need, and the increased Vds
lowers the capacitance of the part in addition to supporting
the higher current with more transconductance. Probably
you will want to reduce the Source resistance in the
process, but I have not determined the specifics.
Having done that, you can safely parallel the cascode
devices, giving each some Source resistance and matching
to ensure sharing, and you will also parallel the current
source transistors on the top, also adjusting their gain
networks appropriately.
The result will be lower distortion and more speed, which
you will need to support higher power.
Thanks for the advice. It will defintely be an interesting experience and i hope to learn enough to be able to play with some of the new SS fets. For now, i would rather make a 3$ part go "pop", than a 25$ part. I am looking at some 12" x 12" heatsinks, even considered putting the LU's on a CPU cooler. Oh well, I hope to jave something to talk about soon.
Forgive my ignorance, but I am trying to figure out this modulation thing. Is the mosfet simply shielding the the Jfet from the voltage and passing the amplified signal from the Jfet to the load, adding nothing, or is taking the signal it receives at its source pin and adding voltage gain. Is the mosfet operating as a common gate amplifier providing the voltage swing while the Jfet acting operating as common source providing most of the current gain with only minimal voltage gain.
Second question; when you say increasing current, Nelson, do you mean increasing bias which increases current through fet. Also, increasing Vds must have a limitation considering the dissipation of the Jfet, especially considering the increased current. So what is the upper limit, i beleive you say in you article that about 10-12W, is any point beyond this where the decision to parallel the Jfets kick in. Just keeping the Vds of 3V and increasing the current to 4A, we are bumping our heads against that dissiption limit.
Sorry for all the questions. I love having the drive to learn again. I wish I could go back and get a second degree.
Second question; when you say increasing current, Nelson, do you mean increasing bias which increases current through fet. Also, increasing Vds must have a limitation considering the dissipation of the Jfet, especially considering the increased current. So what is the upper limit, i beleive you say in you article that about 10-12W, is any point beyond this where the decision to parallel the Jfets kick in. Just keeping the Vds of 3V and increasing the current to 4A, we are bumping our heads against that dissiption limit.
Sorry for all the questions. I love having the drive to learn again. I wish I could go back and get a second degree.
Thinking ahead somewhat, what about an F3 front end driving either an F4 or Circlotron second stage. Xing the whole thing. My Borberly Jfet preamp, got me thinking about it, topologies being similar. Single gain stage F3 would not benefit from Susy as much as combo. Funny, I havenMt even figured out stage 1 and I am thinking about adding second gain stage as well as Susy.
1) Yes on the second part, but the cascode adds very little to the character.
2) Yes also. Get the current up to say, 2 or 3 amps and bump the voltage
up as well to keep capacitance down and gain up. Just keep the Jfet cool.
I have been thinking on this amp some more and have more questions.
1. IS there any benefit to providing the Jfets with their own HS. This would isolate them from the mosfets and keep them from seeing any of the corresponding heat.
2. Looking at the Zen V9 article, the current and cascode fets are already at a pretty high dissipation point (46W), so with any increase in power, they would definitely need to be paralleled almost immediately. I am basing this on HeatSink USA's largest profile. It is the most readily available HS to the average DIYer at a reasonable price.
3. It has been stated that increasing the Vds is important to increase gain and to help deal with capacitance, but should we try to keep the Vds of the individual Jfets (assuming paralleled devices) at around 3V. This seems to be the sweet spot from the graph. I believe it is possible that i am reading the graph wrong concerning this area. In the back of my mind, i keep thinking of voltage swing at the drain of the Jfet, but this is exactly what the cascode modulation is trying to keep from happening, correct. Also, I hear whispers of Ohm's Law in my head and think I am missing something on the sharing of paralleled devices. Paralleled devices all see the same voltage, but share the current......I think. Back to study to refresh my memeory
1. IS there any benefit to providing the Jfets with their own HS. This would isolate them from the mosfets and keep them from seeing any of the corresponding heat.
2. Looking at the Zen V9 article, the current and cascode fets are already at a pretty high dissipation point (46W), so with any increase in power, they would definitely need to be paralleled almost immediately. I am basing this on HeatSink USA's largest profile. It is the most readily available HS to the average DIYer at a reasonable price.
3. It has been stated that increasing the Vds is important to increase gain and to help deal with capacitance, but should we try to keep the Vds of the individual Jfets (assuming paralleled devices) at around 3V. This seems to be the sweet spot from the graph. I believe it is possible that i am reading the graph wrong concerning this area. In the back of my mind, i keep thinking of voltage swing at the drain of the Jfet, but this is exactly what the cascode modulation is trying to keep from happening, correct. Also, I hear whispers of Ohm's Law in my head and think I am missing something on the sharing of paralleled devices. Paralleled devices all see the same voltage, but share the current......I think. Back to study to refresh my memeory
While wating for my F3 parts to arrive, i have been reading up on different articles at the Pass site. It is my hope, as stated before, to use the F3 build as a learning experience. In doing so, I had planned on building it out further in both a high power version and a balanced version. I don't really know yet, since i have not started. Back to the reading. Two articles i found really interesting were the DIY opamp and the PLH article. I am probably wrong, but there seems to be some building blocks ideas in both of these articles that could be helpful in scaling just about any amplifier. Looking at the DIY Opamp article, I see a lot of possibilities for balnced amps as well as front ends. In the PLH article, it seems similar to what is going on in the BAF amps second stage/VAS? Could be, or even probably wrong. We shall see. Thanks for letting me spew!
Looking at what caps to get for the output of the F3. I plan on paralleling multiple caps and cannot decide on the brand. Elna's are recommended by Pass, ut the Nichicon KG series has better numbers. Ripple current is almost double on the KG and from the discussions about the benefits of the caps, low ESR and high ripple current seem to be important. NOne of te datasheets show ESR ratings, that i can see, so ripple current is all that is left. I guess only difference between Silmics and Nichicon is the paper used. Silmics seem to haev an advantage in this area. I would get both, but i cannot afford it. Also, Do i need 15000uF or can I use less without any detriment? I have FR drivers that are 7ohm.
Your question is difficult to unswer from purely technical ground, it more relates to believes and empirical experience. As for my vision, use 15-20 pcs of 1000uF Elna Silmics, it is a tested solution, plus 50-100uF polypropylene shunt cap (or a pair of smaller caps, like 33uF).
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.