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Old 15th March 2011, 11:45 PM   #11
GregH2 is offline GregH2  Australia
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Quote:
Originally Posted by Nelson Pass View Post
Those 20 KHz square waves are not a problem. From the
looks of it, the jittery may be your test equipment.

Thanks Nelson,

I would never have suspected that as the waves look reasonable when the scope is attached directly to the signal generator before the 4.7uF poly input capacitor. If that's the case than the FFT analysis is also going to be pretty useless I would suspect!

Are you suggesting the equipment is inferior or that I am using it incorrectly?

Both are probably true.

I have a conventional CRO too, unfortunately also a cheapie. Will hook it up tonight and see how things look.

Thanks for your comments.

Greg.
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Old 16th March 2011, 10:30 AM   #12
GregH2 is offline GregH2  Australia
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Hmm,

As promised, different sig gen and CRO. Same problem (see photo).

The droopy tail end of the square wave is due to the cheap sig gen and its square wave looks a lot like that anyway. But as far as I can tell the peak at the front of the wave is due to the amplifier.

Gate waveform at jfet input is perfect.

Waveform going into 240 gate stoppers is terrible. If I had ringing at the 240 gates, would this be the case or would I only see bad waveforms after the gate stoppers? Maybe I need bigger gate stoppers here?

Problem is probably in JFET input or CCS. But where and why? PCB layout is pretty good I would think.

Is this something I can fix or am I asking too much of such a simple circuit?

Should I just not bother trying to solve it given that no audio signal will have this kind of rise time?

Thanks again for your help!
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Old 20th March 2011, 06:48 AM   #13
godfrey is offline godfrey  South Africa
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Hi Greg

Aside from the spikes, it looks like you have a nice fast rise time, but relatively slow fall time (although still enough for audio imho). Some possible problems I can think of:

a) C1 in the CCS looks (to my fading eyes) like 0.001uF i.e. 1nF. In conjunction with R5, that's going to slow things down a bit. As an experiment I would try reducing that to maybe 100pF and see what happens to the square wave.

b) The current through J2 may not be high enough to switch off M4 and M5 fast enough. You can measure the voltage across R15 to see what it's idling at. If you put a small resistor in series with J1's drain, you can check the voltage across it with a scope during the square wave test to see if it's clipping i.e. switching off during part of the cycle. Maybe you'll see something that sheds light on the other misbehavior as well.

Another limiting factor may be that there's only about 3mA of current available through R8 and R11 to drive M1 and M2. With fast output voltage swings, M1 and M2 will require quite a bit of gate current due to their gate-drain capacitance.

You could try dropping R8 and R11 to maybe 2.2K each and see what happens. Putting a small resistor in series with Q3's emitter and checking the voltage waveform across it with a scope might also give you a better idea what's going on there.

Cheers - Godfrey

p.s. I wonder how constant the current through J2 actually is. You could check the voltage across R15 with a scope to find out.
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Old 20th March 2011, 07:16 AM   #14
GregH2 is offline GregH2  Australia
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Thanks Godfrey,

I've been waiting for someone to give me some solid feedback about this for a while. Really appreciate your input. Comments below:


Quote:
a) C1 in the CCS looks (to my fading eyes) like 0.001uF i.e. 1nF. In conjunction with R5, that's going to slow things down a bit. As an experiment I would try reducing that to maybe 100pF and see what happens to the square wave.
Yes you read correctly. Good idea, I'll make it smaller.

Quote:
b) The current through J2 may not be high enough to switch off M4 and M5 fast enough. You can measure the voltage across R15 to see what it's idling at. If you put a small resistor in series with J1's drain, you can check the voltage across it with a scope during the square wave test to see if it's clipping i.e. switching off during part of the cycle. Maybe you'll see something that sheds light on the other misbehavior as well.
I was wondering about this. The CCS is biased at 3.5mA which doesn't sound like much. However it is comparable to the bias of each half of the LTP in the Aleph J so I thought it would do.


Quote:
Another limiting factor may be that there's only about 3mA of current available through R8 and R11 to drive M1 and M2. With fast output voltage swings, M1 and M2 will require quite a bit of gate current due to their gate-drain capacitance.

You could try dropping R8 and R11 to maybe 2.2K each and see what happens. Putting a small resistor in series with Q3's emitter and checking the voltage waveform across it with a scope might also give you a better idea what's going on there.
Good idea. I'll try these things and let you know how it goes. I have been wondering how to tweak the resistors values in the current source and your explanation has helped me understand it better.

Quote:
Cheers - Godfrey

p.s. I wonder how constant the current through J2 actually is. You could check the voltage across R15 with a scope to find out.
It's about 3.5mA.

Will report back tomorrow hopefully.

Thanks again,

Greg.
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Old 20th March 2011, 08:29 AM   #15
GregH2 is offline GregH2  Australia
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Godfrey,

As promised I have made some modifications to the circuit. I didn't have a 100pf cap for the ccs cap so I removed it completely. Spikes gone! This causes me to ask, what is the purpose of this cap anyway, and do we really need it?

I also dropped R8 and R12 to 2.5k, but performance is much the same.

Unfortunately the droopy tail is still there, but I think it is probably from too little current in the input stage ccs, as you suggested. I will try replacing the bottom J202 with a J203, which has a much higher current flow at Vgs=0. Unfortunately I don't have any on hand so we will have to wait a week or two.

Here is a scope shot of a 20kHz square wave. Top trace is the input into the top JFET. Bottom trace is the output waveform across a 6R load and through a 10,000uF output cap. A big improvement. As you can see my sig gen isn't exactly a great performer either.

Obviously when unloaded the rise time looks a little better, but the unloaded output isn't what counts, is it?

Thanks again for your help. This has been a very educational experience.
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Last edited by GregH2; 20th March 2011 at 08:41 AM.
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Old 20th March 2011, 09:05 AM   #16
GregH2 is offline GregH2  Australia
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Ah crap! I hooked it up to my other sig gen (a slightly better one) and unregulated PSU, and the peaks are back. Nowhere near as bad as before, but they're there. On a positive note the rise time is much better with the unregulated PSU. Seems the regulated one is too slow.

Last edited by GregH2; 20th March 2011 at 09:26 AM.
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Old 20th March 2011, 09:30 AM   #17
godfrey is offline godfrey  South Africa
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Quote:
Originally Posted by swordfishy View Post
As promised I have made some modifications to the circuit.
Wow, that was fast
Quote:
Originally Posted by swordfishy View Post
...what is the purpose of this cap anyway, and do we really need it?
You're asking me? I didn't put it there!
OK, seriously; a small cap may be needed for stability - in your case it seems not. Anyway a cap that big looks like someone was deliberately trying to slow it down a bit. Thinking about it, the cap decides how fast the CCS wants to react, but the current through R8 and R11 decides how fast it can react.
Quote:
Originally Posted by swordfishy View Post
I will try replacing the bottom J202 with a J203, which has a much higher current flow at Vgs=0.
Can't you just reduce the value of R15 to increase the current?
Quote:
Originally Posted by swordfishy View Post
As you can see my sig gen isn't exactly a great performer either.
Any sig gen and scope is better than none. All I have these days is a multimeter.
Quote:
Originally Posted by swordfishy View Post
Obviously when unloaded the rise time looks a little better, but the unloaded output isn't what counts, is it?
The acid test is loading the output with small capacitors, say 1nF to 10nF. That's what really hurts stability. Don't do like Carlos and blow up your amp trying to drive full power square waves into a 100nF cap though.
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Old 20th March 2011, 09:42 AM   #18
tsz is offline tsz  Sweden
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Hi Greg,

Out of curiosity; have you tried using the positive rail as reference for the input as well (with C5 across R1 instead of R2)?

Also how is the layout of the positive rail done? Where is the speaker return connected? Close to M4, M5?
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Old 20th March 2011, 12:04 PM   #19
GregH2 is offline GregH2  Australia
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Quote:
Originally Posted by tsz View Post
Hi Greg,

Out of curiosity; have you tried using the positive rail as reference for the input as well (with C5 across R1 instead of R2)?

Also how is the layout of the positive rail done? Where is the speaker return connected? Close to M4, M5?

Hi tsz,

No I haven't tried that. Is there any reason to?

The speaker return is connected to ground (unlike the schematic).

The PCB layout is attached (but I'm only using 2 output pairs, not 3).
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Old 20th March 2011, 12:07 PM   #20
GregH2 is offline GregH2  Australia
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Thanks Godfrey,

Quote:
Can't you just reduce the value of R15 to increase the current?
Unfortunately not. It's currently set to 0R, which provides 3.5mA. If I want more current I need to switch fets. I'm going to try a J203.
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