F5X -- the EUVL Approach

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Is the low voltage used in the f5x'es kept that low in order to be able to bias the mosfets higher, or are there other reasons too?
The reason I'm asking is that I'm using active crossovers, using CheffdeGare's UP for the low range and would like to build a cascoded, balanced F5x for the treble. I,ve got all the hardware, but would like to build it using +/-32 Volts. Is there a very good reason not to do so?

Thanks in advance!
 
Yes, so if you use 32V, you bias at say 1A to keep the MOSFETs alive.
You maximum Class A current is 2A.

Say you have 8ohm speakers, you have 16V across the speaker, and hence 8V from each side (left & right) of the X amp.

32-8 = 24V headroom, doing nothing other than burning electricity.

Will work and make (even nice) sound, I am sure.
Just not using the circuit properly..


Patrick
 
Your normal bias is 32V 1A per Mosfet. i.e. 32W.
This is as much as I would dissipate continuously on a TO247 Mosfet.

Assume a 8 ohm speaker at with +/-28V output in balanced mode.
Maximum current is, in theory, 7A.

I'll let you calculate the dissipation of the Mosfets in Class AB based on that.
It will be less than 32x7 = 224W, but it will mostly likely be a lot more than 32W.

If you are happy to take that risk, please go ahead. Don't let me discourage you.

:)


Patrick
 
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Why degenerating the MOSFETs?

I am trying to learn/understand why the MOSFETs in the F5X are degenerated and looking around I have found multiple explanations for using/not-using MOSFET degeneration....

Not being an EE it is difficult for me to understand which of these claims are true and which of these forms the rationale for the implementation of MOSFET degeneration in the F5X.

Claimed effects of degeneration:
1) Make the gain of the circuit more linear.
2) Boosts the output impedance.
3) Provides series feedback.
4) Reduces 3rd order products.
5) Transforms input impedance to be real instead of imaginary.
6) Increase NP-matching accuracy.
7) Decreases the usable output swing.
8) Increases noise.

Any opinions?

Cheers,

Nic
 
We don't parallel MOSFETs in F5x (standard).
So the 0R22 is not for current balancing.

But look at the curve of Id vs Vgs at 25°C in the datasheet.
And check what the current would be at say 75~100°C Junction temp, keeping Vgs constant.

Now add the 0R22, keeping the voltage across Vgs+0R22 constant with temperature.
Check how much the current changes at 75~100°C now.

And please come back and tell the complete story.
Thanks in advance.

:)


Patrick
 
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Joined 2009
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And please come back and tell the complete story.
From data sheet:
@25˚C a 2SK1530 will conduct 2A, when Vgs is about 2.3V
@125˚C, with the same Vgs, the device will conduct roughly 3A

If we add in the 0R22 this will drop the voltage seen by the FET by E = I*R or 2-3A*0R22 = 0.44-0.66V
@ Vgs = 2.3V - 0.44V = 1.9V the FET will conduct 2A @ 125˚C :)

Let me see if I got it wright:
At constant Vgs the current conducted by the FET increases with temperature.
The source resistor lower the Vgs seen by the FET proportionally to the conducted current.
I.e. the source resistor provide negative current feedback, possibly preventing thermal run away.
If the resistor has a positive tempco it will also provide a thermal negative feedback on the current.

I am sure this is not the hole story, but the only piece I think I understand.

Did I pass the exam?
 
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