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Old 23rd February 2011, 07:51 PM   #71
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I did the measurements myself to determine what Idss I need to get around 6mA in the circuit, and those values get you in the ball park.

Last edited by Melon Head; 23rd February 2011 at 07:53 PM.
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Old 24th February 2011, 09:08 AM   #72
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Originally Posted by Melon Head View Post
I did the measurements myself to determine what Idss I need to get around 6mA in the circuit, and those values get you in the ball park.
post65 is quoting model values for a simulator.
This post is talking about measurements and 6mA in circuit.
What are you finding? What are you simulating? What are you measuring?
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Old 24th February 2011, 10:29 AM   #73
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I was interested in the characteristics of gain and freq resp from the std F5. And, what I would end up with by changing the JFET Rdrains, output MOSFET(s), Bias, Rload, etc., etc..
First problem I know about is the model parameters of the 2SK170 and 2SJ74 in my Pspice. They are nowhere near a 6-7mA device. In order to be more accurate with the sim, I need a more realistic model.
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Old 24th February 2011, 07:51 PM   #74
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I am measuring Id vs vgs, Idss, and Id when the part is placed in the circuit.

Patrick said to flg if he lowers the current running through the jfets eg 6mA then he can increase the the drain resistor an hence increase the open loop gain.

I was merely telling him what to adjust to get 6mA. I am not endorsing anything here
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Old 25th February 2011, 03:41 AM   #75
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The original circuits from NP runs at about 6mA at the frontend.

I merely pointed out that if your spice model is at 11mA Idss, it will run in circuit at about 10mA due to 10R source resistor. You lose OL gain and this gives different overall results. And Dave kindly offered you tips how to change it back to 6mA.




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Old 27th February 2011, 10:17 AM   #76
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I have been able to spend a little time simmimng with Ppsice. Keep in mind YMMV
I used Melon Head's suggested modification to the JFET model and it seems to be working more like we want. I made a test circuit that has about 6.5mA Iq in the front end with a volatge gain of about 34. The JFET drain resistors adjusted to about 740 ohms. I tried to keep passive components and everything faithull to the F5. Completeing the circuit a pair of un-modified IRFP240 and 9240s with 1.3A bias.
The stock F5 shows OLG of about 333 with an 8 ohm load and OL BW is -3db @ 63kHz. Closed loop gain measures about 5.88 and has a -3db of 3MHz!
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Old 27th February 2011, 10:33 AM   #77
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The stock F5 shows OLG of about 333 with an 8 ohm load and OL BW is -3db @ 63kHz. Closed loop gain measures about 5.88 and has a -3db of 3MHz!
yes, for a single pole roll off, the OLG/CLG * OLBW ~= CLBW or 333/5.88 * 63k ~ 3.6MHz.

This is another way of using that phrase "gain bandwidth" is constant.
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Old 27th February 2011, 11:25 AM   #78
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Where is the second corner frequency in open loop ?


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Old 27th February 2011, 02:36 PM   #79
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Where is the second corner frequency in open loop ?

Patrick
Very hard to tell. Appears to not have one at least to Unitty gain of about 25MHz
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Old 27th February 2011, 03:08 PM   #80
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I assume you have a plot of OLG vs Freq. After the first corner freq the OLG has -6dB slope. After the second, it has -12dB. So you cannot miss. If you do not see a change of slope in OLG all the way up to 0dB (at which point OLG drops to 1 from 333), then the amp is unconditionally stable even at unity gain. But I doubt that. You could also look at the phase and see where you change from 0 to 90 to 180.


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