F5 For Low Z Loads ?

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Using my eyes, as a percentage change, say from 20-10Vds they look very similar. And not as rediculous as is sometime depicted.
So, a 16V rail, as you have chosen, does seem quite viable.


22v would be better ...

You will change the sound by paralleling output devices as you changed the total capacitances that the input stage has to drive, and hence the open loop frequency response. Yes, you will get some of it back in close loop as your open loop gain also increases. But this is like opamps which has the first open loop corner frequency at well below 1kHz. i.e. the circuit has to work increasingly harder with frequency above 1kHz.

While the F5 is not my design, I try to layout closed loop circuits such that the first open loop corner frequency is above 20kHz. That way I can get away with low loop NFB (<=30dB).


Patrick

Hmmm........
 
I did some sims some time ago but, nobody wants to here that bla bla do they. Keep in mind it's only as good as the models and sim. My 2sks are about 11mA in the model and I only have a IRFP240/9240 with who knows what parameters.
The front end has very little gain as I remember and that makes sense. The output I think was most of the gain of 300. I did not do much higher level stuff, but, now that Patrick suggests this looks like a 741, I should go look at OLG and freq responce etc. and see what we have here...
UUUUURGH! :Pawprint:
 
If you lower the frontend current to 6mA, you will double the frontend gain (with the same 2nd stage bias).
You need to know how to change your Spice model to do this.
Contact Melon Head for details. I am sure he is very willing to help.

And yes, look at OLG & fre resp, like an opamp.
Bob Cordell's book also have a very good section on this.

;)


Patrick
 
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Early in the eighties I was the front end guy for Motorola OpAmps. I think I can dig it out. I should look into Bob's new book though. Looks like a good investment.
I can probably figure out the Spice thing enough for a ballpark idea where we're goin with this. Something about those claims of MHz response made me think I didn't really need to think about that much, if I tried to stay faithfull to the original design? But, OpAmps do that too, under some conditions. It was a little surprising to see a Pass design with so much gain and F.B.?
Melon Head, are you listening? (Never stops making me laugh, when I see that. I'm talking to a Melon Head!). I need a little time though. I'm free tonight but, I really wanted to play with some heatsink testing tonight...
:Pawprint:
 
DuKnow? But, I beleive Euvl had posted some measurements some time back of actuall devices in this regard. Probably associated with his tweeking of the F5 input satge? I'm not sure that would be to easy to find though? And deffinately not while I'm workin :D
 
I might get a chance to play with the sim tonight? Depends on what the S.O. wants to do. But, I really want to finish setting up my Heat Sink testing ideas first. Once things are cooking, I can play Pspice...
Any ideas about Lambda, Vgsth, and anything else I'm not thinking about now?
What about a model for the 1530 and 201?
:Pawprint:
 
I was interested in the characteristics of gain and freq resp from the std F5. And, what I would end up with by changing the JFET Rdrains, output MOSFET(s), Bias, Rload, etc., etc..
First problem I know about is the model parameters of the 2SK170 and 2SJ74 in my Pspice. They are nowhere near a 6-7mA device. In order to be more accurate with the sim, I need a more realistic model.
:Pawprint:
 
I am measuring Id vs vgs, Idss, and Id when the part is placed in the circuit.

Patrick said to flg if he lowers the current running through the jfets eg 6mA then he can increase the the drain resistor an hence increase the open loop gain.

I was merely telling him what to adjust to get 6mA. I am not endorsing anything here
 
The original circuits from NP runs at about 6mA at the frontend.

I merely pointed out that if your spice model is at 11mA Idss, it will run in circuit at about 10mA due to 10R source resistor. You lose OL gain and this gives different overall results. And Dave kindly offered you tips how to change it back to 6mA.

;)


Patrick
 
I have been able to spend a little time simmimng with Ppsice. Keep in mind YMMV :D
I used Melon Head's suggested modification to the JFET model and it seems to be working more like we want. I made a test circuit that has about 6.5mA Iq in the front end with a volatge gain of about 34. The JFET drain resistors adjusted to about 740 ohms. I tried to keep passive components and everything faithull to the F5. Completeing the circuit a pair of un-modified IRFP240 and 9240s with 1.3A bias.
The stock F5 shows OLG of about 333 with an 8 ohm load and OL BW is -3db @ 63kHz. Closed loop gain measures about 5.88 and has a -3db of 3MHz!
:Pawprint:
 
I assume you have a plot of OLG vs Freq. After the first corner freq the OLG has -6dB slope. After the second, it has -12dB. So you cannot miss. If you do not see a change of slope in OLG all the way up to 0dB (at which point OLG drops to 1 from 333), then the amp is unconditionally stable even at unity gain. But I doubt that. You could also look at the phase and see where you change from 0° to 90° to 180°.


Patrick
 
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