Mezmerize DCB1 Building Thread

[Salas]

The ones you already use are not matched at all? Just random?

P.S. Try using some tamer LEDS for the 10.61V section in the group of five so to bring it a bit nearer 10V. That should help you finally judge your now offset better.

[pmchoong]

Hi,

What is the worst case scenario if none of the fets are matched? I have some sk170 which I don't think they are matched and I intend to build the mesmerize with these fets.

Thanks.
Pmchoong

[Salas]

To have excessive DC offset that will warrant an output capacitor coupler and a bit more THD maybe. Depends on chancing to the constant current fet over driving the signal fet above it.

[pmchoong]

1) Which means if the Fets aren't matched :

1) you will get a very high DC offset and that will blow the output capacitor. Is this correct?

Or :

2) you will get a higher than normal DC offset, overwork the output capacitor (thus shortening its lifespan) and maybe the THD would be a little higher too.

But the sound quality remains the same.

Thanks.
PMChoong

Originally Posted by Salas

To have excessive DC offset that will warrant an output capacitor coupler and a bit more THD maybe. Depends on chancing to the constant current fet over driving the signal fet above it.

[Salas]

This is optimally a full DC coupled buffer. If it will show enough output offset it will need be blocked with a capacitor. That is all. Capacitors are to block DC up to their rating printed on them. They are not in danger doing that, its one of their normal jobs.

[dimkasta]

The possible problem I mentioned above would appear while measuring voltages in the range of mV using the V scale in the multemeter.
Try setting the new multimeter to the mV range scale and then measure the offset again, just to be sure

[rokoko]

Hello Salas,
I have seen on “Toshiba 2SK170BL for sales” some DIYs requesting from Spencer 8.5mA matched 2SK170, or even matched to 9mA Idss.
Is there a particular reason for this, would JFETs with higher Idss at 0Vgs have better linearity, less distortions?

One more thing to ask, if I would like to have a more safe approach and add DC blocking cap on the output, and the input resistance of my Power Amp is 20kOhms, what cap value would be OK, can you also recommend a good cap chemistry-P/Number.

[Salas]

At 9mA there is 90mW to dissipate for each Jfet as we use it here and better don't go higher for long term reliability, there is enough transconductance already. THD differences from say 7-9mA are not drastic.
Use 6.8uF I would say. Prices and subjective evaluations vary widely but an Obbligato MKP oiler, the one in black can with flying leads should be economical and effective since you need some uF.

[rokoko]

Salas, thanks so much for your quick reply. Few more things to ask.
Also higher value, like 10uF should also work? Voltage, any voltage should work, 400V for example? Would 400V Jantzen metallized polypropylene be adequate choise? The conection point, is is OK to:
1. Connect cap between the 220 Ohm resistor (and the relay flying contact? In other words cut the trace between 220 Ohm resistor right lead on schematic (left one is connected to midle point of two JFETs) and insert it between relay. In this case the right side of the cap goes to the output through relay contact and the is connected to GND through existing 1M resistor?
2. Or to connect/insert a cap between the 1 MOhm resistor and output connector, adding another 1M resistor to the GND on connector side, the output to the power amplifier?

[Salas]

Yes on all points except (1) which is false.