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Old 10th September 2010, 06:06 PM   #21
frags is offline frags  Canada
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Andy5112405,

Try my method. Get LM317 with multiturn trimmer to adjust voltage between 4 and 6V.
Connect it to unregulated 12V DC (I used 12V acid battery from an UPS). Connect 2R5 resistor between drain/gate point and LM317 Vout. Mount the FET at a heatsink as well. Adjust Vout at the regulator to have 1V drop across the resistor (400mA via the resistor and FET). You need to adjust it only once for all FETS. Now change FETS and measure the drops across the resistor. The difference in drops at the resistor will show the same difference in Vgs for different FETs.
You don't need to wait for FETs to warm up themselves and heatsink.

I used this method to choose IRFP240s for Aleph J bougth from mouser and got 1-2mV Vgs difference for most of them.
Then I got the current distribution between paralleled FETs within 0.5%

Last edited by frags; 10th September 2010 at 06:14 PM.
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Old 11th September 2010, 01:26 PM   #22
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Thanks Frags, I'll try it.

At the moment I am using the method suggested by Andrew T. I'm using ONE MOS-FET connected as a REFERENCE with a 10R resistor in its DRAIN leg to monitor the current through the REF. With every other FET connected, one at a time, I can adjust the Vgs until the REF is passing 400mA. The temperature is pretty consistent as I'm using the amplifiers massive heatsinks. With Tcs = 25 Deg C +/- 1 Deg C and Is (REF) = 400mA, I'm getting Is (TEST) between 121mA and 419mA over a range of 35 MOS-FETs.

It's not a temperature issue, as, after I have adjusted Vgs to achieve Is(REF) = 400mA. The device under TEST continues to share its portion of current at a fairly constant figure even after 5 minutes on the Jig.

The only thing I can think of is that REF has a sil-pad fitted whilst TEST is mounted directly to the heatsink. As the two DRAINS have to be isolated.

I'm wondering if I've bought 50 rejects from someone elses matching efforts.
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Old 11th September 2010, 01:54 PM   #23
AndrewT is offline AndrewT  Scotland
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I don't think you have rejects.
If you look at the datasheet for the spread of Vgs at test current you will find it is surprisingly large. If you turn this back to front, you can get an idea of the spread of Id for a fixed Vgs. It is an enormous spread. It seems to be a production problem.

Your results of Id=121 to 419mA are typical of production Power mosFETs. That's why parallel pairs, or more, must be matched.
The Vgs vs Id is a very varied parameter.

Now pick two DUTs that appear to have the same Id at that REF Vgs and you should find they match fairly closely. As the DUT test current moves away from the REF Id the batch grouping becomes wider. But you can still compare DUTs to each other.

The Method helps remove variations Tj and Time from the measurements.

Now you can take the matching further. I do not do this with Power FETs, but I do it with jFETs.
Adjust the REF Vgs and measure how well the DUT Id tracks the REF Id. These were a surprise when I first started, now I know that a number of parameters need to matched to get good tracking between pairs. I can't match the parameters, I don't even know how to measure them, but by trial and error I can get good and sometimes superlative tracking with some pairs.
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Old 11th September 2010, 04:19 PM   #24
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Checking my results in a spreadsheet, I've only tested 35 of the 50 MOS-FETs I can group them quite happily within 10% of each other. Hopefully with the remaining devices things might get a bit tighter.

Is there any ruling about the matching of the 4 banks ? ie LH Amp / LH Current Source / RH Amp / RH Current Source as the groups are quite different.

Last edited by Andy5112405; 11th September 2010 at 04:20 PM. Reason: Even I haven't got nearly 600 MOS-FEETs
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Old 11th September 2010, 04:31 PM   #25
AndrewT is offline AndrewT  Scotland
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Quote:
Originally Posted by Andy5112405 View Post
Checking my results in a spreadsheet, I've only tested 35 of the 50 MOS-FETs I can group them quite happily within 10% of each other.
when you fit them in circuit with a Source resistor they will Id match even closer.
Vbias=Vgs+Vrs
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Old 12th September 2010, 01:38 PM   #26
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OK so I've now got 50x Ids at accurate Vgs.

Is it better to keep all the 24 MOS-FETs fairly close and accept 20% variation in matching, or is it better to have closely matched sextuplets which are wildly different from the other groups.

Does that make sense?

I can have 24 MOS-FETs which are all within 40% of each other, each group of 6 is within 15% of each other. Or I can have 24 MOS-FETs within nearly 200% of each other but each sextet is within 10%.
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Old 12th September 2010, 02:55 PM   #27
Zen Mod is offline Zen Mod  Serbia
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upper bank - one sextet - closely matched

lower bank - one sextet - closely matched

double that for other channel

conclusion - 4 different sextets , and you need matched ones strictly on sextet basis
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Old 13th September 2010, 10:27 AM   #28
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Using FRAGs suggestion of feeding the Vgs via an LM317 I've now got 4 x groups of 6 mos-FETs. Group 1 matched to within 2.9%, Group 2 = 1.0%, Group 3 = 3.2% and Group 4 = 7.7%, I've also got a spare Group = 11.3%.
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Old 13th September 2010, 11:09 AM   #29
AndrewT is offline AndrewT  Scotland
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groups 1 to 3 are superb.
group 4 is good. You will need matched source resistors to reliably measure the installed differences in bias current.

Split the spare group into triples or pairs for future use.
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Old 3rd June 2011, 01:46 PM   #30
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After a bit of a break I'm now at the stage of building the Output Boards for my Aleph 4.

Testing the individual boards has shown that the matching process was pretyy good.

On board 1 I have Ids within 0.7% for 6 MOS-FETs
On board 2 0.5%
On board 3 2.0%

Board 4 is yet to be tested.

Which boards would be better as Current Source (Bottom Board) and which the Amplifier (Top Board)
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