F5 with 2SK2013/2SJ313

[Zen Mod]

Originally Posted by umut1001

I did not see your message and write it i deleted a min ago

naah - you didn't must ........

fun in learning is even greater when we are able to laugh together ;

I'm still able to embarrass my self in public - every day ...... and I have fun in that

that's real brain-storming - say whatever you need to say ........ when day is good , that will lead in most wakoo ways .........

[umut1001]

I fried 3 pairs of mosfets (because of oscillation) at F5. i do not want to fry again

[GuidoR]

While waiting for the little Toshibas to come from Zhoufang (10 weeks lead time ), I’ve been attracted (and who has not?) from this Balanced F5 question thread, so I thought to a 313/2013-based version. The attached schematic comes directly from that thread, and the values of R1/R101 and R2/R102 (widely commented) so as R7/R8 and R9/R10 are copied from EUVL’s schematic (see attached), so consider them as tentative values.
Is this beast feasible? Are there alternative values of supply voltage / idle current that could be considered in order to achieve the “sweet spot” or even lower the overall dissipation (at the price of a lower max power output)?
I’m aware of dissipation issues, so we (in fact, I’m representing a bunch of ardent DIYers) are already thinking to a very ambitious (for us) case, but this is another story (another case, in fact ).

Juma (or any other), could you comment please?

Guido (poor Padanian Man)

[massimo]

Wow!

massimo (poor and padanian as well)

Edit: input network missing in both schems. 1 k in series and 100 k to ground?

[Zen Mod]

Forza Vale !

[juma]

GuidoR,
I would do it like this:
- lower PSU voltage, +/-16V max.
- 4 pairs of k2013/313 per side (8 pairs per channel)
- Id set at 0.5A through each MOSFET

[GuidoR]

Juma,
Thank you for your reply.
However, my target is to reduce dissipation, not to increase it.
What about 3 pairs @ 0,5A? (keeping in mind cost-benefit ratio, following ZenMod's PSM policy )

And furthermore, what is your opinion about FB resistors' value? Difference between the lower and upper half or standard 50 Ohm for both as in F5?

Guido

[juma]

That way you'll have lower bias, meaning less A class power. Having an 16 Ohms speaker would be nice with lower Id.

No reason to use asymmetrical FB resistors. Amount of feedback is yours to choose - listening tests will tell you do you prefer less feedback/more distortion or vice versa.

[GuidoR]

No high Z but high efficiency (I'm a proud owner of a couple of Altec VOT ), so no need for more power. In fact, I was thinking to a balanced xed 30 watter, even if more complicated than the SE version.

Thanks

Guido

[NYCOne]

Guido -

This is very much like what I was thinking of doing. I like Juma's idea about 4 pairs of outputs on each side.

I've also been trying to chase down the IRFP balanced XF5. How do you optimize the resistors around the outputs for any device? It seems like this knowledge would be useful in trying a number of outputs.

Originally Posted by GuidoR

While waiting for the little Toshibas to come from Zhoufang (10 weeks lead time ), I’ve been attracted (and who has not?) from this Balanced F5 question thread, so I thought to a 313/2013-based version. The attached schematic comes directly from that thread, and the values of R1/R101 and R2/R102 (widely commented) so as R7/R8 and R9/R10 are copied from EUVL’s schematic (see attached), so consider them as tentative values.
Is this beast feasible? Are there alternative values of supply voltage / idle current that could be considered in order to achieve the “sweet spot” or even lower the overall dissipation (at the price of a lower max power output)?
I’m aware of dissipation issues, so we (in fact, I’m representing a bunch of ardent DIYers) are already thinking to a very ambitious (for us) case, but this is another story (another case, in fact ).

Juma (or any other), could you comment please?

Guido (poor Padanian Man)