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Old 30th April 2010, 10:21 AM   #11
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Hey Vladimir,

The actíve devices looks very interesting, do you have any datasheets that isn´t in russian?

How do you get away with two CCS´s on top of each other? A cascode is also to be looked upon as one? Normally it isn´t so easy to deal with as the DC-voltage at the cascode output could be all over the place.
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Old 30th April 2010, 11:15 AM   #12
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Quote:
Originally Posted by revintage View Post
Hey Vladimir,
The actíve devices looks very interesting, do you have any datasheets that isn´t in russian?
How do you get away with two CCS´s on top of each other? A cascode is also to be looked upon as one? Normally it isn´t so easy to deal with as the DC-voltage at the cascode output could be all over the place.
Hello, Lars
I can only enclose the CP650 datasheet, that is similar to KP903.
As of KP926, it is a high-voltage (450V, 16A) SIT transistor designed 20 years ago, when it was considered to be good for switch power converters. It has triode-like Id vs Vds, quite a big Idss (I guess 2500pF), I dissipated 50W of heat on them during measurements. They like high voltages. Not many of them have big enough Id(Ugs=0) nearly 1A at Uds=10V, some of them could be even closed at Ugs=0. For several amps Id, they must be operated as BJT transistors with positive Ugs. One russian designer (Konstantin Musatoff) used them with 300V power supply, low currents and output transformer.

In this preamp schematics there is only one CCS, it is in fact a simplified Zen9. The top KP926A acts as a CCS only conditionally, its properties something between a simple resistor and a real CCS. If interesting, I can prepare and enclose its Id vs Uds in the CCS configuration.
Attached Files
File Type: pdf CP650-653 n-chan 20V 0,6A 8W.pdf (98.5 KB, 114 views)

Last edited by VladimirK; 30th April 2010 at 11:19 AM.
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Old 30th April 2010, 01:47 PM   #13
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Excuse me for a typo error in the previous post, Idss is to be read as Ciss (gate capacitance)
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Old 30th April 2010, 04:41 PM   #14
flg is offline flg  United States
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I have the translated pararmeters if you would like them. I just have to find them... You can guess at most of them...
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Old 10th May 2010, 02:12 AM   #15
Jen-B is offline Jen-B  United Kingdom
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Originally Posted by VladimirK View Post
Voltage gain with a connected load of 1,3kOhms is 12,2 (22dB). Square wave response at 70V p-t-p, 100kHz, 1k3 load is shown in the foto.
Hello Vladimir, I am trying to learn about your preamplifier circuit... my understanding is that the max input is limited to 1.6V peak by the gate-to-source bias. Then 1.6V x 12.2 (gain) x 2 (for peak to peak) = 39V peak to peak. So I do not understand how you produce an output of 70V peak to peak? I am a beginner with design... so is there a simple answer for me?

Thank you,
J.
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Old 10th May 2010, 04:22 AM   #16
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Quote:
Originally Posted by Jen-B View Post
Hello Vladimir, I am trying to learn about your preamplifier circuit... my understanding is that the max input is limited to 1.6V peak by the gate-to-source bias. Then 1.6V x 12.2 (gain) x 2 (for peak to peak) = 39V peak to peak. So I do not understand how you produce an output of 70V peak to peak? I am a beginner with design... so is there a simple answer for me? Thank you,
J.
Hello, Jen
The Ugs=1,6V indicated in the schematics is a design estimate, actual precise value should be measured, what I still have to do.
Inspite of this, the CP 650 j-fet has something near 8V pinch-off gate-to-source voltage, and also allows operation with positive gate bias. Total acceptable swing of Ugs approaches 10V. This can explain the reported behaviour of the schematics.
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Old 10th May 2010, 05:02 AM   #17
Jen-B is offline Jen-B  United Kingdom
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Vladimir, thanks for the quick answer. I will take another look at the circuit, and the datasheet of the CP650, and learn some more.
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