according to post #2030 , I can see few things :
increase R28 to have 1V5 across R6 ; then you'll have around 1V across R29
then fiddle with P1 to have 0 at R16/R17 node
increase source resistors for input Jfets , to have 9V4 at Q3 colector
solid caps are rarely culprit of problems , at least not in this range of voltage
all measurements with input gnd-ed
if you make it as Wayne constructed it , it must work
if not - something is ooked in actual physical layout
frankly - I can't keep up with this thread , but it seems that Pearl make more than one Greedy Boy suffer ...... and that's pity , bcs circuit is simple and elegant and easy to grasp
increase R28 to have 1V5 across R6 ; then you'll have around 1V across R29
then fiddle with P1 to have 0 at R16/R17 node
increase source resistors for input Jfets , to have 9V4 at Q3 colector
solid caps are rarely culprit of problems , at least not in this range of voltage
all measurements with input gnd-ed
if you make it as Wayne constructed it , it must work
if not - something is ooked in actual physical layout
frankly - I can't keep up with this thread , but it seems that Pearl make more than one Greedy Boy suffer ...... and that's pity , bcs circuit is simple and elegant and easy to grasp
frankly - I can't keep up with this thread , but it seems that Pearl make more than one Greedy Boy suffer ...... and that's pity , bcs circuit is simple and elegant and easy to grasp
..unless you are Greedy Boy in Training (GBIT), newb. Probably over complicating - comes down to mistake in stuffing,etc. Bad component due to previous mistake. A lot bad ZVP3310s, ZTK450s for a lot of Greedy Boys, GBIT.
When I layed out the Pearl Two allowance was made for a lag capacitor around the ZVP3310. After building more of them I find it is not needed. I suggest you just leave it out. Your mileage may vary if you roll your own boards or change parts. Saves finding a good 10 PF cap.
As an experiment try R16 at 100K. Also on one version I built, C7 caused oscillation. Remember it isn't fixed until you can break it and fix it at will.
The DC flip flop can be oscillation caused.
Sounds like I should pull C7.
I read this before building it - need to carve a half a day and re-read the entire thread.
Pearl (first version, not Pearl II)
LINK TO TESTS OF PEARL MK I
LINK TO TESTS OF PEARL MK I
An externally hosted image should be here but it was not working when we last tested it.
Pulling C7 seems to have fixed my issue. DC offset very stable on both channels > +/- 20 mv. No oscillation.
Those trannsistors in the vendors must be different enough inside by now than what Wayne compensated in the original design then...
Milosz. Nice tests, data. Ready to build a Pearl 2?
Don't need the extra gain.
Suggest to read Bob Cordell's Audio PAmp book p226, this may better explain whats going on. One way or the other you have managed to figure out how to make the circuit oscillate.
I just read, Mosfets are fast and prone to oscilliation. Discusses topologies to combat (Gate Zobel network). Does not discuss effect of lag cap around MOSFET and oscillation like the Pearl 2. Wayne has experienced as well and recommends eliminating cap around Mosfet. Not going to worry how I (and others including Wayne) managed to make the circuit oscillate.
Not going to worry how I (and others including Wayne) managed to make the circuit oscillate.
What's the saying...
"If you want to build an amplifier, you will likely get an oscillator.
If you want an oscillator, you will likely get an amp. "
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