Lets do not assume anything
Based on Nelson's comment, these new jFets are straight replacement for the N channel Mosfets. Which one R100 or R500? J2 schematic is not available and Nelson is not going to publish it soon. My interest is in use in F3, donut F3, or BA amp.
as I wrote today , and I hope that you received at least one e-mail .........
http://www.diyaudio.com/forums/pass...p170r550-better-building-amp.html#post2076321
In practice there is very little difference between the R100 and
R125 versions for our applications. I get just about the same
numbers in the J2's with either part.
btw. if you look here ( search fro Papa's posts in recent time ) :
diyAudio - Search Results
there are some interesting things .
especially this :
http://www.diyaudio.com/forums/pass...p170r550-better-building-amp.html#post2078145
.........
With regard to JFETs, there are more parts coming out in
time, so patience will be rewarded.
edit :
if you need more information ( especially these brought to me by my Black Adder in Pass Labs
) , we can do this in vivo ...... typing is tiresome 
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if you need more information ( especially these brought to me by my Black Adder in Pass Labs
You know, there are a few lucky people in this world and I am one of them...
Having friend like you...
Even though if it sounds like a perfect text for the Hallmark card, I mean it!
that will be extremely easy , taking in account all breadcrumbs Papa already gave regarding J2 .
anyway - as I wrote few times before , I'll not do that in public , taking in account another thing - my impression that Papa isn't so willing to see another prompt Babelfish .
but - we can always count on his witty character , he'll probably reveal some new toy , then J2 will not be too much important , so probably freely explorable area .
not important to him - completely understandable ;
not important to greedy boyz (always chasing next Graal ) - pretty sad fact
You know, there are a few lucky people in this world and I am one of them...
Having friend like you...
Even though if it sounds like a perfect text for the Hallmark card, I mean it!
now you made me
pulling Zen Mod , Duke of Modesty , to leg .......
as I said - there are several issues with straight implementation of SS Jfets instead of Mosfets , all pretty much solvable ( again courtesy of Wizzard of FWozz) ..... but I'm too lazy to :
- bring all relevant quotes in one post ,
- pretend that any of tips is actually mine ("see how clever I am "
)-try to extend my limited knowledge of most important of three R's ....... at least in English , to be sure that anyone is in fact catching what I meant to say .....
edit :
Wizzard of FWozz already gave ( in one extraordinary long 5-liner post) all necessary explanations for details of J2 , including differences to Aleph J ;
I'll make you pancakes if you sneak in his storage and read what's written on small 6-legged creature on pcb , just to catch last drift of J2 humor ;
I mean - I know how to make voltage source for output totem pole bias , but finding exactly why he choose actual part is essence of fun ........ and sometimes even funnier is realizing that choice of part is pure random act ......
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Simple, Candrive SiC JFET?
......
sure - why not
......
I just want ideas on tweaking existing designs to support devices better.
double input jfets , double current through their CCS , decrease input LTP drain resistor for 2x(4/1,25) amount , and you have starting point for both linear behaving of input LTP and good slew rate blahblah
toss Aleph CCS , make output stage as in J2 basic schematic , make (adjustable) voltage source(reg) between gates - in value as one PSU leg , to linearize things further put two appropriate resistors between lower drain and upper source , take output between them . appropriate resistors are sub-ohmic
don't forget gate stoppers for all gates
anyway - Papa already wrote all that , and more .
even using J pcbs , it will be more tossing parts out , than putting them in
...
...
Sausage boy, Sausage
Dosen't N.P. have a pattent for an Opto Isolator in the bias network? Didn't he use that somewhere many moons ago? They sometimes have 6 legs??? Hmmmm?read what's written on small 6-legged creature on pcb... ...actual part is essence of fun ........ and sometimes even funnier is realizing that choice of part is pure random act ......
I think so far, I like the idea of doubling input Jfets and ccs on BA1 front end, and running normal 'bias section' with ztx450 critter and IRF240's on .6v lower half. (I think FLG idea) running R100 on V+.
From BA1 article
There is also a bias system for the negative half of the output stage formed by R216, R217,
R218, R219, C207 and Q204. Q204 is a generic NPN transistor which sees the voltage
appearing across the 1 ohm Source resistors of the negative half of the output stage and sets
their value at about 0.6 volts, locking them in at a constant current value of 0.6A each.
Alternatively, I can run the output standalone, all R100's, drive it with Pumpy, see what happens.
Then I can work more on different output stage for BA1 thing with/ without magic bipolar transistor.
From BA1 article
There is also a bias system for the negative half of the output stage formed by R216, R217,
R218, R219, C207 and Q204. Q204 is a generic NPN transistor which sees the voltage
appearing across the 1 ohm Source resistors of the negative half of the output stage and sets
their value at about 0.6 volts, locking them in at a constant current value of 0.6A each.
Alternatively, I can run the output standalone, all R100's, drive it with Pumpy, see what happens.
Then I can work more on different output stage for BA1 thing with/ without magic bipolar transistor.
Well, I hear some confusion in there somewhere? I'm thinking I'm building a jfet output Aleph J. but we are in a J2 thread There are similarities and N.P. has solved similar challenges to get to the J2. So far, I plan to use dual input JFETs on the input stage. Maybe dual on the input stage CCS JFETs too. Otherwise very similar to an Aleph 3 or J or the BA gain stage. The Drain Load resistor on the input stage will need to be down around 200-250 ohms vs. maybe 1k in an Aleph. This lowers the gain, but, the paralelling of JFETs increases the gain. The reason for this smaller load resistor is the lower Vth of the power JFET output transistors. You maybe need a bias of 1.8V at the Gate of the output transistor vs. 4.6V with an IRF240 type device. You should also be maintaining good bandwidth with a lower source resistance than an Aleph front end and the lower capacitance of the power JFET output devices.
I'm thinking I will build the standard Aleph CS with IRF240type devices on top of the Sic power JFET gain devices. 1 pair of power JFETs per ch.
There are similarities and N.P. has solved similar challenges to get to the J2. So far, I plan to use dual input JFETs on the input stage. Maybe dual on the input stage CCS JFETs too. Otherwise very similar to an Aleph 3 or J or the BA gain stage. The Drain Load resistor on the input stage will need to be down around 200-250 ohms vs. maybe 1k in an Aleph. This lowers the gain, but, the paralelling of JFETs increases the gain. The reason for this smaller load resistor is the lower Vth of the power JFET output transistors. You maybe need a bias of 1.8V at the Gate of the output transistor vs. 4.6V with an IRF240 type device. You should also be maintaining good bandwidth with a lower source resistance than an Aleph front end and the lower capacitance of the power JFET output devices. I'm thinking I will build the standard Aleph CS with IRF240type devices on top of the Sic power JFET gain devices. 1 pair of power JFETs per ch.
I also thought of keeping the upper Aleph current source, just leaving the original fet... This would have the fortunate effect that we only need 1 Semisouth device per channel...
To ease drive requirements:
If we cascode the 2sj109 with a small power mosfet (610 or so...) we could crank up the current and keep within the dissipation specs. Maybe it would linearize further as well.
I personally dislike the BA amps compared to F3, J2, because they're more conventional and lack Papas holy simplistic approach... ;-))
Regs Dirk
To ease drive requirements:
If we cascode the 2sj109 with a small power mosfet (610 or so...) we could crank up the current and keep within the dissipation specs. Maybe it would linearize further as well.
I personally dislike the BA amps compared to F3, J2, because they're more conventional and lack Papas holy simplistic approach... ;-))
Regs Dirk
If you double the p-JFET input stage, and use IRFP240 + only 1 SiC JFET for output stage, the cost will not be that much lower.
With double input jfet, it take 4 2sj74 (2 pairs, if not a quad) for every channel.
And 4 matched 2sj74 (not to mension 2 x j109) is currently not much cheaper than 1 SS SiC JFET.
As time goes by, the cost of 2sj74 will likely be going up while cost of SiC devices (if they are still jfet) will go down.
I wish Linear tech can keep their promise and deliver their LSJ74 + LSJ109, or else options for everyone will be very limited.
Regarding increasing the Bias current of j109/j74 to increase their transconductance,I think it is a good idea if you have an high IDSS jfet, otherwise the effect will be limited. As currently we mostly only have BL grade for j109/j74, the bias is limited in the first place, and transconductance Only if you get the high end of BL grade, or V grade, then thermal dissipation might start to be the limiting factor.
With double input jfet, it take 4 2sj74 (2 pairs, if not a quad) for every channel.
And 4 matched 2sj74 (not to mension 2 x j109) is currently not much cheaper than 1 SS SiC JFET.
As time goes by, the cost of 2sj74 will likely be going up while cost of SiC devices (if they are still jfet) will go down.
I wish Linear tech can keep their promise and deliver their LSJ74 + LSJ109, or else options for everyone will be very limited.
Regarding increasing the Bias current of j109/j74 to increase their transconductance,I think it is a good idea if you have an high IDSS jfet, otherwise the effect will be limited. As currently we mostly only have BL grade for j109/j74, the bias is limited in the first place, and transconductance Only if you get the high end of BL grade, or V grade, then thermal dissipation might start to be the limiting factor.
due to smaller Ugs of SS Jfets , comparing to IRFPs , Papa must decrease drain resistor in input LTP ; say that 5mA through each input Jfet is sorta sweet current and - to keep that , along with adequate load line (read - gain of stage) for each half of LTP , seems to me that doubling number of input Jfets is clever thing ;
looking just on capacitances of SS Jfet , comparing to plain vanilla IRFP , seems that Jfet is easier to drive , but who knows why Papa decided for increased headroom ...
anyway - making CCS feed for input LTP with Jfets ..... looks as waste , but I'm pretty sure that Papa have drekload of these
, so why not ....... if overall Tempco is better that way ...By putting 2x p-jfet, we increase the gain by 1.4x while keeping the bias current and drain resistor all the same, am I right?
And this being a gain problem due to the smaller Vth of output device, rather than a driving capability problem due to the high input capacitance of the output device, even if we will to parallel the SiC output device, we don't really need to increase the number of input p-jfets, do we?
One thing I never understand is that why Nelson did not put a drain resistor in the negative input (dummy) side of the input LTP? This seems to be the standard, not just in J2.
Won't putting a drain resistor there make the Vds of the LTP equal, reduce the thermal dissipation power of the two sides to an equal, and thus reach thermo-equivalent, and ultimately making the two side more symmetrical and produce less distortion?
They are dirt cheap compared to the p-Jfet or SiC JFET. Toshiba is still making them at least once a month.
For anyone who need a dozen of these to build some CCS, I can give you these 170 for free, provided you come to my place and collect yourself. Anyone from high northern latitude wants to enjoy some tropical Sunshine? You can get these 170 jfet as a bonus.
And this being a gain problem due to the smaller Vth of output device, rather than a driving capability problem due to the high input capacitance of the output device, even if we will to parallel the SiC output device, we don't really need to increase the number of input p-jfets, do we?
One thing I never understand is that why Nelson did not put a drain resistor in the negative input (dummy) side of the input LTP? This seems to be the standard, not just in J2.
Won't putting a drain resistor there make the Vds of the LTP equal, reduce the thermal dissipation power of the two sides to an equal, and thus reach thermo-equivalent, and ultimately making the two side more symmetrical and produce less distortion?
Are you talking about the parallel 2sk170?
They are dirt cheap compared to the p-Jfet or SiC JFET. Toshiba is still making them at least once a month.
For anyone who need a dozen of these to build some CCS, I can give you these 170 for free, provided you come to my place and collect yourself. Anyone from high northern latitude wants to enjoy some tropical Sunshine? You can get these 170 jfet as a bonus.
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dunno ; I have ear-ache/problems for a week now , so I'm somewhat fuzzy and grumpy
anyway - just calc gain (Rd/(1/S+Rs) with 1S and 2S , with various Rd and math is ...... math .
so everything seems as plain logic - to maintain load line for input parts and have right voltage for cranking up SS Jfets
yeah - you are correct regarding everything further in above quote . anyway - disclaimer - as I wrote - I'm dumb ZM as usual , so I can't decrypt all Papa's weird reasons
maybe I'm odd or weird , but I really see humor in his constructions , and for me that quality is even more important than tech part of his conribution to DIY community ....
in every book I read ( NB that I don't have formal education in electronic) regarding that topic - I understood that with omitting that "other" resistor is good for linearity etc. what is really important for balance and linearity is "tail length" ......
anyway - that "other resistor" position is crucial one for implementing of another funny creature - called ''folded cascode'' ; just look at schematic of Mighty ZM's Babelfish J , and you'll see example of pathetic
ZM's attempt to implement folded cascode in LTP .http://choky.diyaudio.rs/images/Babelfish J bal.gif
it seems pity that we aren't somewhat closer ; not because of free 2SK .... ( who need them , when you always substitute them with anything laying on the bench .... even if I have them - I'll not use them in that position , because of my weird principles
) ....... but because it seems as fun , possibility to hang around and chat in vivo ..... 
O.K. so, moving along... Is there a Source resistor in the lower output transistor of the J2? I would say, of course, he always uses one It will linearize the operating curve, control/reduce gain, stabalize the thermal and Iq properties (if you run a pair, it will help with the equalizing and matched operation) and raise the necessary bias needed at the gate node. Maybe some other effects I'm not thinking of ??? And N.P. would probably say, it is a convineant place to measure bias current.
O.K., and if so, what size? Ordinarily I would go with the N.P. would... thing but I think the SiC JFET may be a little different animal? I beleive there is some rule of thumb
Maybe based on the Source R overwelming the chages in Channel R? or something. The resistor developes a voltage across it that is some pecentage of the threshold voltage. Basically averaging in a more linear voltage drop with the more nonlinear junction if you will. In this case the threshold voltage is not 4V like most N.P. stuff, it's 1.25V or something. The Iq through the output transistor is roughly typical N.P. current though. This would likely necessitate a smaller Rsource
Any ideas in this area???
It will linearize the operating curve, control/reduce gain, stabalize the thermal and Iq properties (if you run a pair, it will help with the equalizing and matched operation) and raise the necessary bias needed at the gate node. Maybe some other effects I'm not thinking of ??? And N.P. would probably say, it is a convineant place to measure bias current. O.K., and if so, what size? Ordinarily I would go with the N.P. would... thing but I think the SiC JFET may be a little different animal? I beleive there is some rule of thumb
Maybe based on the Source R overwelming the chages in Channel R? or something. The resistor developes a voltage across it that is some pecentage of the threshold voltage. Basically averaging in a more linear voltage drop with the more nonlinear junction if you will. In this case the threshold voltage is not 4V like most N.P. stuff, it's 1.25V or something. The Iq through the output transistor is roughly typical N.P. current though. This would likely necessitate a smaller Rsource Any ideas in this area???