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Old 18th February 2010, 11:36 PM   #451
flg is offline flg  United States
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Well, I hear some confusion in there somewhere? I'm thinking I'm building a jfet output Aleph J. but we are in a J2 thread There are similarities and N.P. has solved similar challenges to get to the J2. So far, I plan to use dual input JFETs on the input stage. Maybe dual on the input stage CCS JFETs too. Otherwise very similar to an Aleph 3 or J or the BA gain stage. The Drain Load resistor on the input stage will need to be down around 200-250 ohms vs. maybe 1k in an Aleph. This lowers the gain, but, the paralelling of JFETs increases the gain. The reason for this smaller load resistor is the lower Vth of the power JFET output transistors. You maybe need a bias of 1.8V at the Gate of the output transistor vs. 4.6V with an IRF240 type device. You should also be maintaining good bandwidth with a lower source resistance than an Aleph front end and the lower capacitance of the power JFET output devices.
I'm thinking I will build the standard Aleph CS with IRF240type devices on top of the Sic power JFET gain devices. 1 pair of power JFETs per ch.
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Old 19th February 2010, 10:09 AM   #452
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I also thought of keeping the upper Aleph current source, just leaving the original fet... This would have the fortunate effect that we only need 1 Semisouth device per channel...

To ease drive requirements:

If we cascode the 2sj109 with a small power mosfet (610 or so...) we could crank up the current and keep within the dissipation specs. Maybe it would linearize further as well.

I personally dislike the BA amps compared to F3, J2, because they're more conventional and lack Papas holy simplistic approach... ;-))

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Old 19th February 2010, 04:29 PM   #453
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If you double the p-JFET input stage, and use IRFP240 + only 1 SiC JFET for output stage, the cost will not be that much lower.
With double input jfet, it take 4 2sj74 (2 pairs, if not a quad) for every channel.
And 4 matched 2sj74 (not to mension 2 x j109) is currently not much cheaper than 1 SS SiC JFET.
As time goes by, the cost of 2sj74 will likely be going up while cost of SiC devices (if they are still jfet) will go down.
I wish Linear tech can keep their promise and deliver their LSJ74 + LSJ109, or else options for everyone will be very limited.

Regarding increasing the Bias current of j109/j74 to increase their transconductance,I think it is a good idea if you have an high IDSS jfet, otherwise the effect will be limited. As currently we mostly only have BL grade for j109/j74, the bias is limited in the first place, and transconductance Only if you get the high end of BL grade, or V grade, then thermal dissipation might start to be the limiting factor.
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Old 19th February 2010, 05:10 PM   #454
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Quote:
Originally Posted by zhoufang View Post
If you double the p-JFET input stage, and use IRFP240 + only 1 SiC JFET for output stage, the cost will not be that much lower.
With double input jfet, it take 4 2sj74 (2 pairs, if not a quad) for every channel.
And 4 matched 2sj74 (not to mension 2 x j109) is currently not much cheaper than 1 SS SiC JFET.
As time goes by, the cost of 2sj74 will likely be going up while cost of SiC devices (if they are still jfet) will go down.
I wish Linear tech can keep their promise and deliver their LSJ74 + LSJ109, or else options for everyone will be very limited.

Regarding increasing the Bias current of j109/j74 to increase their transconductance,I think it is a good idea if you have an high IDSS jfet, otherwise the effect will be limited. As currently we mostly only have BL grade for j109/j74, the bias is limited in the first place, and transconductance Only if you get the high end of BL grade, or V grade, then thermal dissipation might start to be the limiting factor.
due to smaller Ugs of SS Jfets , comparing to IRFPs , Papa must decrease drain resistor in input LTP ; say that 5mA through each input Jfet is sorta sweet current and - to keep that , along with adequate load line (read - gain of stage) for each half of LTP , seems to me that doubling number of input Jfets is clever thing ;


looking just on capacitances of SS Jfet , comparing to plain vanilla IRFP , seems that Jfet is easier to drive , but who knows why Papa decided for increased headroom ...

anyway - making CCS feed for input LTP with Jfets ..... looks as waste , but I'm pretty sure that Papa have drekload of these , so why not ....... if overall Tempco is better that way ...
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Old 19th February 2010, 06:06 PM   #455
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By putting 2x p-jfet, we increase the gain by 1.4x while keeping the bias current and drain resistor all the same, am I right?
And this being a gain problem due to the smaller Vth of output device, rather than a driving capability problem due to the high input capacitance of the output device, even if we will to parallel the SiC output device, we don't really need to increase the number of input p-jfets, do we?

One thing I never understand is that why Nelson did not put a drain resistor in the negative input (dummy) side of the input LTP? This seems to be the standard, not just in J2.
Won't putting a drain resistor there make the Vds of the LTP equal, reduce the thermal dissipation power of the two sides to an equal, and thus reach thermo-equivalent, and ultimately making the two side more symmetrical and produce less distortion?

Quote:
Originally Posted by Zen Mod View Post
making CCS feed for input LTP with Jfets ..... looks as waste
Are you talking about the parallel 2sk170?
They are dirt cheap compared to the p-Jfet or SiC JFET. Toshiba is still making them at least once a month.
For anyone who need a dozen of these to build some CCS, I can give you these 170 for free, provided you come to my place and collect yourself. Anyone from high northern latitude wants to enjoy some tropical Sunshine? You can get these 170 jfet as a bonus.

Last edited by zhoufang; 19th February 2010 at 06:31 PM.
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Old 19th February 2010, 10:09 PM   #456
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Quote:
Originally Posted by zhoufang View Post
By putting 2x p-jfet, we increase the gain by 1.4x while keeping the bias current and drain resistor all the same, am I right?
And this being a gain problem due to the smaller Vth of output device, rather than a driving capability problem due to the high input capacitance of the output device, even if we will to parallel the SiC output device, we don't really need to increase the number of input p-jfets, do we?

....
dunno ; I have ear-ache/problems for a week now , so I'm somewhat fuzzy and grumpy

anyway - just calc gain (Rd/(1/S+Rs) with 1S and 2S , with various Rd and math is ...... math .
so everything seems as plain logic - to maintain load line for input parts and have right voltage for cranking up SS Jfets

yeah - you are correct regarding everything further in above quote . anyway - disclaimer - as I wrote - I'm dumb ZM as usual , so I can't decrypt all Papa's weird reasons
maybe I'm odd or weird , but I really see humor in his constructions , and for me that quality is even more important than tech part of his conribution to DIY community ....

Quote:
Originally Posted by zhoufang View Post
......
One thing I never understand is that why Nelson did not put a drain resistor in the negative input (dummy) side of the input LTP? This seems to be the standard, not just in J2.
Won't putting a drain resistor there make the Vds of the LTP equal, reduce the thermal dissipation power of the two sides to an equal, and thus reach thermo-equivalent, and ultimately making the two side more symmetrical and produce less distortion?

.....
in every book I read ( NB that I don't have formal education in electronic) regarding that topic - I understood that with omitting that "other" resistor is good for linearity etc. what is really important for balance and linearity is "tail length" ......
anyway - that "other resistor" position is crucial one for implementing of another funny creature - called ''folded cascode'' ; just look at schematic of Mighty ZM's Babelfish J , and you'll see example of pathetic ZM's attempt to implement folded cascode in LTP .
http://choky.diyaudio.rs/images/Babelfish%20J%20bal.gif

Quote:
Are you talking about the parallel 2sk170?
They are dirt cheap compared to the p-Jfet or SiC JFET. Toshiba is still making them at least once a month.
For anyone who need a dozen of these to build some CCS, I can give you these 170 for free, provided you come to my place and collect yourself. Anyone from high northern latitude wants to enjoy some tropical Sunshine? You can get these 170 jfet as a bonus.

it seems pity that we aren't somewhat closer ; not because of free 2SK .... ( who need them , when you always substitute them with anything laying on the bench .... even if I have them - I'll not use them in that position , because of my weird principles ) ....... but because it seems as fun , possibility to hang around and chat in vivo .....
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Old 20th February 2010, 04:22 AM   #457
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Thank you Zen Mod for the explanation!
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Old 20th February 2010, 01:22 PM   #458
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ZM and FLG have been helpful in understanding much of what is needed to get pieces of the puzzle in order. Thanks!

Now just to see if I can make a drekless amp out of it...Even if it's clearly not J2 clone.
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Old 20th February 2010, 03:36 PM   #459
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O.K. so, moving along... Is there a Source resistor in the lower output transistor of the J2? I would say, of course, he always uses one It will linearize the operating curve, control/reduce gain, stabalize the thermal and Iq properties (if you run a pair, it will help with the equalizing and matched operation) and raise the necessary bias needed at the gate node. Maybe some other effects I'm not thinking of ??? And N.P. would probably say, it is a convineant place to measure bias current.
O.K., and if so, what size? Ordinarily I would go with the N.P. would... thing but I think the SiC JFET may be a little different animal? I beleive there is some rule of thumb Maybe based on the Source R overwelming the chages in Channel R? or something. The resistor developes a voltage across it that is some pecentage of the threshold voltage. Basically averaging in a more linear voltage drop with the more nonlinear junction if you will. In this case the threshold voltage is not 4V like most N.P. stuff, it's 1.25V or something. The Iq through the output transistor is roughly typical N.P. current though. This would likely necessitate a smaller Rsource
Any ideas in this area???
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Old 20th February 2010, 04:04 PM   #460
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say that 20% of Ugs across Rs isn't insane ;

say that upper two resistors are each 50% of (lower ) Rs

say that PSU is twice 22-voltish ( plain vanilla 36Vct or 2x18V xformer )

say that current is 2A
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