schematic variation and sim results of Pass "X" series US pat 5376899
2 Attachment(s)
Two unbal. power amp vers based of Pass "X" (SuSy) with sim. results (Fig. 3 from US patent 5376899)
I have read the article about USPatent 5376899 All topology versions from there you can find by http://www.pat2pdf.org (please fill in 5376899 before download) Short form describtion about the basic schematics from Fig. 14 Fig 1: singleended foldedcascode voltage gain stage/current source, inverting mode Fig.2: complementarysymmetry version of foldedcascode voltage gain stages, inverting mode Fig.3 and Fig.4: same as Fig. 1 and 2, but include push pull power follower, that is in NFB loop All versions from Fig. 14 are balanced versions, i. e. to use only for bridged mode. I looked by "circuitmaker" at some relationships between two NFB variations and THD at low and high frequencies. At bottom the results  but please note, that is not really an orig. Xmodel, because I choise unlal. (unbridged) version. Please note secondly follow: by this simulation all capacitors and resistors so as the voltage source (power supply) and input source (signal generator) are idealized (i. e. no internal resistance by the power supply). In additional there are no lead respective wire inductance and spread capacitance through PCB layout. Only the effects of pure circuit  are to see. In real life (few years ago) only version with lower current and voltage I have tested (I have used as evaluation unity gain preamplifier with additional compensation capacitor)  so beginners should not be evaluate and not trying for diy. Proffesionals should be use excellent high performance heatsinks, even by the MOSFETs for the voltage amplifier (my rule is follow: heatsink temperature above ambient: < 20 degrees  aprox the same value as my hands) Also of interest it could be, whether there are great differences by simulation results in other cad software (e.g. Orcad, Microsim or LTspice). Perhaps one of you this one can check out because the circuit is very simple. Following parameters are valid for all versions: Voltage gain = 10times, input 1Vss, output 10Vss, wave form: sine wave. Both PDF images are directly comparable, after performing download of all pdf files. My simulations based on the unbridged version of Fig. 3 of us patent 5376899 for inverting mode matched for 60 VDC single ended power supply. I choise a unsymmetrical power supply, so I don't have trouble with dc offset so as dc speaker protection. Both versions I have simulated also with single ended power follower version, but the difference compare to pushpull version is not to observe by 2 times of idle (quiescent) current though the SE output. A good feature is to work with variable source resistor for choise the open loop gain (possible through two independend current source) Follow sequence for the Images I have choise: A: Pass X unbal. Var. I NFB incl. PPoutput 1) schematic for Damping factor test 2) ACAnalysis (damping factor over frequency) 3) AC Analysis (normally frequency response) 4) Fourier Analysis lin 10 KHz (THD) K2: 9mV K3: 10,5mV K5: 0,54mV 5) Fourier Analysis log 10 KHz (THD) 6) Fourier Analysis lin 100 KHz (THD) (K2: 75mV K3: 74mV) 7) Fourier Analysis log 100 KHz (THD) 8) Fourier Analysis log 19/20 KHz (IM) 9) Transient Analysis 1MHz 10) schematic No 9) only to observe, if there are  sawtoothdeforming (risk of TIM, in generall still present by NFB about two voltage gain stages)  or not critical and audible low passdeforming (no risk of TIM, only delay in setting time) 
2 Attachment(s)
Two unbal. power amp vers based of Pass "X" (SuSy) with sim. results (Fig. 3 from US patent 5376899) continued
B: Pass X unbal. Var. II PPoutput not in the NFB loop 1) schematic for Damping factor test 2) ACAnalysis (damping factor over frequency) 3) AC Analysis (normally frequency response) 4) Fourier Analysis lin 10 KHz (THD) K2 25mV K3: 11,5mV K4: 1,94mV 5) Fourier Analysis log 10 KHz (THD) 6) Fourier Analysis lin 100 KHz (THD) K2: 190mV K3: 70mV K4: 7,8mV 7) Fourier Analysis log 100 KHz (THD) 8) Fourier Analysis log 19/20 KHz (IM) 9) Transient Analysis 1MHz 10) schematic No 9) only to observe, if there are  sawtoothdeforming (risk of TIM, in generall still present by NFB about two voltage gain stages)  or not critical and audible low passdeforming (no risk of TIM, only delay in setting time) 
Since the point of the patent is the balanced feedback, did you
happen to model that? :cool: 
hallo Mr. Pass
yes, therefore I must introduce the second bridge half so as two additional resistors connected to the two ends of the existing resistor (for the presently setting of wanted open loop gain) to earth (GND). But the question is, which value is the best choise; there are no dc and signal about the resistor by identical halves but in real life flows the correction current for the distortion cancellation through residual tolerances between both bridge halves. It is interesting to know, what happens, if I introduce tolerances in one bridged half  but it can take some time. I think 23 weeks. I am happy, if you can give me advices about the values regarding these resistors. Perhaps in this time I have some comparative results of simulation from some other members (e. g. j.carr or j.curl), in order to assess how accurate is the modeling of my. Unfortunately I don't know enough about the handling with ORCAD, LTspice or MICROSIM to compare the results. All the best Andreas Kirschner 
Andreas
Are you kidding? Anyway that is not the way to behave. Cheers 
Quote:

Play nice, you boys.
Don't make me come over there. :cool: 
2 Attachment(s)
Four unbal. power amp bal. versions based of Pass "X" (SuSy) with sim. results (Fig. 3 from US patent 5376899)
hallo Mr. Pass here the results of simulation, now for bal. versions. Please note, that I must find solution for GND by simulation. Now there are "actually GND" and "GND only for simulation" by all 4 versions. Please not in additional, that the basic circuit is that of Fig. 3 of US patent 5376899, but device numbers are from Fig 1 respective from first fig. on page 1 of this one. From Var. II and III I don't get the spectrum of IM. Instead of this I get the message "simulation errors occured"  "warning: line too long" Evaluation, analysis and compare to unbal versions I will make the next days. A: Pass X bal Fig3 Var I Gain=10x: 40=100R 36/37=15K OpenLoop Gain: 28x In/out 1V/10Vss 1) schematic for Damping factor test 2) ACAnalysis (damping factor over frequency) 3) AC Analysis (normally frequency response) 4) Fourier Analysis lin 10 KHz (THD) K3: 4,2mV 5) Fourier Analysis log 10 KHz (THD) 6) Fourier Analysis lin 100 KHz (THD) (K3: 15,4mV) 7) Fourier Analysis log 100 KHz (THD) 8) Fourier Analysis log 19/20 KHz (IM) 9) Transient Analysis 1MHz 10) schematic 
2 Attachment(s)
Four unbal. power amp bal versions based of Pass "X" (SuSy) with sim. results (Fig. 3 from US patent 5376899) continued
D: Pass X bal Fig3 Var IV Gain=83x: 40=20R 36/37 = NC (15M) OpenLoop Gain: 83x In/out 120m/10Vss 1) schematic for Damping factor test 2) ACAnalysis (damping factor over frequency) 3) AC Analysis (normally frequency response) 4) Fourier Analysis lin 10 KHz (THD) K3: 11mV 5) Fourier Analysis log 10 KHz (THD) 6) Fourier Analysis lin 100 KHz (THD) (K3: 27mV) 200mVss input 7) Fourier Analysis log 100 KHz (THD) 200mVss input 8) Fourier Analysis log 19/20 KHz (IM) 9) Transient Analysis 1MHz 10) schematic Unfortunately I must reduce the capacity of pdf files from version II and III, therefore this comes later 
2 Attachment(s)
Four unbal. power amp bal versions based of Pass "X" (SuSy) with sim. results (Fig. 3 from US patent 5376899) continued
B: Pass X bal Fig3 Var II Gain=28x: 40=100R 36/37= NC (15M) OpenLoop Gain: 28x In/out 355m/10Vss 1) schematic for Damping factor test 2) ACAnalysis (damping factor over frequency) 3) AC Analysis (normally frequency response) 4) Fourier Analysis lin 10 KHz (THD) K3: 12,3mV 5) Fourier Analysis log 10 KHz (THD) 6) Fourier Analysis lin 100 KHz (THD) (K3: 25mV) 680mVss for 10Vss 7) Fourier Analysis log 100 KHz (THD) 680mVss for 10Vss 8) Fourier Analysis log 19/20 KHz (IM) 9) Transient Analysis 1MHz 10) schematic 
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