Don't know, never tried. The 220R should limit current. Be my guest crash testing.
Yes, of course it'll mute, but the transistor will be pushing current thru the series output resistor. I want to make sure when that happens, it doesn't go past the resistor's and the transistor's safe limits. I guess the only way to make sure is to measure the V across the resistor while the output is shorted.
The people here have done just that. Had been driving amps with a pot before. Its isolation paying some benefit.
So I suppose that if you have raised the default CCS to, lets say 250mA, that would be the max current?
Wouldn't the maximum current be the IDSS?
What mostly concerns me is burning the output 2SK170 by too much current through it.
As can be seen, I am a noob in transistor matters
shorted output DCB1
assuming that you have 220R gate stopper and 220R output resistor, and the relay shorts at the RCA output jack (so that output 220R is still in the circuit between the FET and the shorting relay), with a signal of say 2Vrms input and volume pot all the way up, then G-S junction of upper FET can become forward biased and conduct. peak current would be approx 2V * 1.414 / (220R +220R) = 6.4mA. The spec for 2sk170 is 10mA max gate current, so i'd recommend to make the gate and or output resistors bigger (say 470R for gate stopper and 330R on output res) to limit gate current to less than 3mA. still might let the magic smoke out of the parts though
lower CCS fet should be OK (as others have eluded to), as its normally seeing about 10V DS anyway and should be dissipating about 100mW, assuming about +-10V symmetric supply. regarding the upper FET's drain current and power dissipation, i'd have to think about it some more...
assuming that you have 220R gate stopper and 220R output resistor, and the relay shorts at the RCA output jack (so that output 220R is still in the circuit between the FET and the shorting relay), with a signal of say 2Vrms input and volume pot all the way up, then G-S junction of upper FET can become forward biased and conduct. peak current would be approx 2V * 1.414 / (220R +220R) = 6.4mA. The spec for 2sk170 is 10mA max gate current, so i'd recommend to make the gate and or output resistors bigger (say 470R for gate stopper and 330R on output res) to limit gate current to less than 3mA. still might let the magic smoke out of the parts though
lower CCS fet should be OK (as others have eluded to), as its normally seeing about 10V DS anyway and should be dissipating about 100mW, assuming about +-10V symmetric supply. regarding the upper FET's drain current and power dissipation, i'd have to think about it some more...
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The DCB1 is recommended and implemented with an opening relay, not a shorting to ground one. Now if someone has a need to temporarily short its output while fully driven etc. might risk the circa 6ma if forward biased by the signal, or up the buffering resistors value to the detriment of its subjective dynamics. Could use a further 220R on the grounding switch though and minimize risks by letting a little more signal through the next stage as most ground mute switches on gear do, leaving some little monitoring.
The key assumption you're making is that muting/shorting occurs while at full signal. That's NOT what I expect. This will happen when there's little or no signal present. Then I think it'll be very safe to do.
My reasoning for this is to eliminate a relay contact point that's normally in the signal path ALL the time. (I realize it's not feasible with the board traces as they are now). This way, the relay is normally shorting to gnd for a few seconds during power-up, then is out of the signal path during normal listening.
My reasoning for this is to eliminate a relay contact point that's normally in the signal path ALL the time. (I realize it's not feasible with the board traces as they are now). This way, the relay is normally shorting to gnd for a few seconds during power-up, then is out of the signal path during normal listening.
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looking for DCB1 schematic
Salas,
can you please point me to the schematic for the DCB1? i thought it was posted somewhere on this thread but i can find it. i'm curious as to why the DCB1 needs output spike protection at power on-- is it something to do with the regulator turn-on characteristics as the rail voltage rises?
thanks,
tincanear
aka Bruce W.
Salas,
can you please point me to the schematic for the DCB1? i thought it was posted somewhere on this thread but i can find it. i'm curious as to why the DCB1 needs output spike protection at power on-- is it something to do with the regulator turn-on characteristics as the rail voltage rises?
thanks,
tincanear
aka Bruce W.
Ian described the main reason right. Beyond avoiding common pops on power up, the DC coupled circuit runs a short cycle of raised offset as its PSUs discharge not tracking each other exactly. So a little time to settle on power up and a fast release on power down is just what the doctor have ordered.
question about salas' shunt reg pos
salas,
from the post (page 1 or 2) for the plusreg, it looks like Q6 is connected "backwards"-- i'm assuming that the fets are physically designed assymetrically (that behavior is different when S & D leads are swapped). For N-ch FET, wouldn't one want to connect the S and G together instead of G & D to make current source and also ensure that D is more positive relative to S&G ? or was it intentionally wired this way?
-tincanear
salas,
from the post (page 1 or 2) for the plusreg, it looks like Q6 is connected "backwards"-- i'm assuming that the fets are physically designed assymetrically (that behavior is different when S & D leads are swapped). For N-ch FET, wouldn't one want to connect the S and G together instead of G & D to make current source and also ensure that D is more positive relative to S&G ? or was it intentionally wired this way?
-tincanear
Its intentional. Creates different currents through the +/- shunts Leds, hence a little different voltages and manipulates the distortion profile in the way I liked it in 2008, since any kind of B1 will distort progressively as it ups level anyway. Some guy saw the manipulation opportunity again and asked here not a long time ago. http://www.diyaudio.com/forums/pass...symmetrical-psu-b1-buffer-88.html#post2053070. It can be put orthodoxically if middle leg is bend and soldered to S off board. Some did it and told me that they put it back. I give the orthodox way to those who use Hypno as a general shunt reg in the respective guide.