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Old 24th June 2010, 09:45 PM   #1581
Salas is online now Salas  Greece
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Nice & detailed account of your thoughts and actions. Keep us posted.

P.S. Shortening the output to ground has a toll on the audio fets, I hope that with the 220R buffer resistors the current will be just OK not to kill any ever. 50K pot for now keeps it back in sonics. A 10k-20k even cheap carbon will do better until you will optimize the LSPD.
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Old 25th June 2010, 02:54 AM   #1582
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Hi.I bought Alien dac v 1.1 and it has direct pcm2702 outputs.At the output there are 47uf coupling capacitors.I do not like them.Can i short circuit the capacitors and use B1 buffer directly?What happens then?Thanks
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Old 25th June 2010, 03:01 AM   #1583
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Don't know about your DAC. Its a question for the digital forums. In general if you have a DC component free line level low impedance output, you can use any DC coupled pot & buffer after.
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Old 25th June 2010, 09:02 AM   #1584
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Quote:
Originally Posted by umut1001 View Post
At the output there are 47uf coupling capacitors.I do not like them.Can i short circuit the capacitors
Hi,
measure the DC offset after and before the coupling capacitors.
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Old 25th June 2010, 10:51 AM   #1585
oenboek is offline oenboek  Belgium
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I don't really see why shortening the output to ground could kill a jfet. I describe what I think happens:
Q1
  • Acts as a current source, so no issue at all, current IDS will remain at IDSS. VDS is well below limits at any time.
Q2:
  • Current through the fet (ID) is limited by the jfet design if I'm not wrong.
  • Voltage over the jfet (VDS): never more then V+, which is +10V.
  • Tension on the gate (VGS): can have full volume from the source, say between + and -2V. At 2V with Rin 220Ohm, gate-current could become 9mA which is below the spec of 10mA gate current. Although I don't see how a gate could draw such a current.
Please let me know where I'm wrong.
I could put an extra resistance to the ground during mute, but it would need to be extremely low value to protect the poweramp from DC. So in practice useless.
I checked the DC offset voltage on startup while it was not shorted to gound, there was no peak showing that both power supply sides went up simultaniously. I'll put a scope to check in detail, I'll do it with a full volume sinewave on the input.
I can as well raise the start-up delay of my poweramp, but I try to have every part self-contained and not depending on another part.
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Old 25th June 2010, 11:13 AM   #1586
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Hi.Firstly i will build the dac.And then i will measure.I could not see any information about dc offset of pcm 2702 outputs in datasheet.But i think B1 buffer will be good for my application(pcm2702 is not a very good dac i do not know it worths though).Thank you
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Old 25th June 2010, 11:22 AM   #1587
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Has anyone tried B1 buffer at the output of Tda1541 chip?
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Old 25th June 2010, 11:46 AM   #1588
Salas is online now Salas  Greece
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Quote:
Originally Posted by oenboek View Post
I don't really see why shortening the output to ground could kill a jfet. I describe what I think happens:
Q1
  • Acts as a current source, so no issue at all, current IDS will remain at IDSS. VDS is well below limits at any time.
Q2:
  • Current through the fet (ID) is limited by the jfet design if I'm not wrong.
  • Voltage over the jfet (VDS): never more then V+, which is +10V.
  • Tension on the gate (VGS): can have full volume from the source, say between + and -2V. At 2V with Rin 220Ohm, gate-current could become 9mA which is below the spec of 10mA gate current. Although I don't see how a gate could draw such a current.
Please let me know where I'm wrong.
I could put an extra resistance to the ground during mute, but it would need to be extremely low value to protect the poweramp from DC. So in practice useless.
I checked the DC offset voltage on startup while it was not shorted to gound, there was no peak showing that both power supply sides went up simultaniously. I'll put a scope to check in detail, I'll do it with a full volume sinewave on the input.
I can as well raise the start-up delay of my poweramp, but I try to have every part self-contained and not depending on another part.
* Building a symmetrical psu B1 buffer

**The DC component rises during shut down.
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Old 25th June 2010, 11:54 AM   #1589
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oenboek, try to measure DC offset and then start blowing air on the board. You will see how DC offset decreases to 0 and then raises on the other polarity. In fact, DC offset of this circuit is caused by thermal drift of its components, not by the circuit design.

Nice idea of thermally coupling both transistors.

Regards,
Regi
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Old 26th June 2010, 01:17 PM   #1590
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Dear salas,
Increasing the number of LEDs from D4-D8 will increase the voltage output? i am needing a good design like yours to regulated at around 15Vdc output.

Regards
chong
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