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Nelson Pass 31st August 2008 09:32 PM

Mosfet Output Stage Capacitance
I was leafing through one of my older notebooks today and
came across something you may like.

A number of you have asked about the trade-offs in
paralleling power Mosfets, particularly driving the Gate
capacitances. Practically speaking, we are talking the
Gate-to-Source and Gate-to-Drain capacitances.

As we parallel devices, we linearly increase the transcon-
ductance, Cgs and Cgd of the parts. Neglecting Cds, the
amount of current it takes to drive the Cgs is proportional
to Cgs and inversely proportional to the transconductance.

There is a considerable cancellation which helps out when
paralleling devices.

The Cds does not go away and remains proportional.

When you look at the spec sheets on these devices, you will
see typical figures quoted, but at Vgs of 0 volts, which is
not typical of the conditions we will see in a linear amplifier.

For the IRFP240 and the IRFP9240 we see a Ciss (total input
capacitance) of 1300 pF and 1400 pf respectively. For the
reverse transfer capacitance Crss the figures are 93 pF and
140 pf respectively.

In linear operation, though, the numbers are different.

Let's take an example of a complementary follower output
stage using 4 parallel pairs of IRFP240 and IRFP9240 with
.47 ohm Source resistors and biased at 100 mA each (400 ma

By carefully measuring the Gate current of each device at
8 volts rms into 8 ohms (1 amp rms) at 1 KHz, 10 KHz, and
100 KHz we can measure the total input capacitance. By
performing the same experiment without a load, we can separate
out the Cgd.

Under these conditions the total input capacitance of the
IRFP240 is about 75 pF and the IRFP9240 is about 60 pF.

Without a load, these figures are 45 pF and 35 pF respectively.

So if you're driving an 8 ohm load with 4 pairs of these
devices, you can estimate your apparent output stage
capacitance at (75+60)*4 pF = 540 pF. Keep in mind that you
won't get 135 pF if you try to drive the 8 ohms with just a
single pair, as the Cgs will will have to be charged to a higher
voltage to make up for the loss of transconductance.

Zen Mod 31st August 2008 10:51 PM

slidin' in Santa Clothes , too early ?


flg 31st August 2008 11:12 PM

Yes, thank you :D

EUVL 1st September 2008 05:23 AM

Thank you for sharing.

May I ask one question.

Suppose I use ONE single pair, but increase the bias to 400mA per FET, and at the same time reduce the source degeneration resistor by a factor of 4. Assuming of course that dissipation is not an issue, for the sake of the discussion.

At such "low" bias currents, one can count on that transconductance is roughly proportional to bias (quadratic region), i.e. 4x per FET compared to 100mA. In which case I would expect the voltage required to drive the gate to be comparable to 4 pair @ 100mA. Would I then not get close to 135p, give or take 20% ?


flg 1st September 2008 02:12 PM

I've been working (playing) with the F4 in the sim, so I thought I would see what Pspice say's about these examples. :smash: :smash: :smash:
All numbers are Pk, not rms, not Pk-Pk :D

In the tradition of First Watt, I set-up a 4V sinewave Output, into 8 ohms (1 Watt Pk), with an F4 looking circuit that contains 4 pairs of IRFP240 and 4 of IRFP9240. I Also did the same for a circuit with only one pair of outputs. The 4 pair of outputs were biased at 100mA Iq ea. with .47 ohm Rs and the single pair circuit biased at 400mA with .1175 ohm Rs...
Is this the circuit in question Patrick?
The 4 pair circuit measures .083% THD @1kHz. The Gate current for each N FET measures about 6uA (Pk) and the Ps about 5.5uA.
The single pair circuit measures .028% THD @1kHz (mostly 2nd harmonic). It's gate current is about 6.5uA into the N gate and 6.3 into the p channel device.
Hmmmm :scratch: :scratch: :scratch:
I don't see a big difference there (as patrick said "give or take 20% ?") :bigeyes:
I suppose a higher frequency may have been a more appropriate parameter to use here???
But, from my previous experiance, the THD numbers are very proportional to the low bias currents. Notice the single pair circuit has less THD??? It has 4X the bias current/FET.
Being not unlike other DIYer's, I also did the same sims with a 20V Pk output. Note, that we are now entering Class AB territory.
The 4 pair circuit measures .092% THD @1kHz. The Gate current for each N FET measures about 30uA (Pk) and the Ps about 28uA.
The single pair circuit measures .165% THD @1kHz (including 2nd, 3rd, a little 4th, 5th and 7th). :bawling: It's gate current is about 32uA into the N and P gates.
More questions???

lineup 1st September 2008 02:31 PM

the irf hexfet shows rather low combined input capacitance
according to Nelson first post investigation
in a real circuit

the resulting input capacitance is something like 10% of Ciss data

is this a value we can use as some 'rule of the thumb'
for most HEXFET / Vertical MOSFET

is this a value we can use as some 'rule of the thumb'
for most LATERAL MOSFET, too

Reasoning that ... even lateral mosfet with their lower Ciss data
should maybe show some 10% ONLY in a real circuit.
I am most interesting of True Class A complementary operation.
As I now post again, in Pass Labs


flg 1st September 2008 02:54 PM

Naturaly, I should have made some irresponsible discloser regarding my post above, claiming all statements were made with honest intent and all, but, I am in no way responsible for errors or actuall circuit behaviour. Rid me of the anti simers and their complaints. In other words, your actual mileage may vary :D
I did however notice a 2-3% gain loss in the single pair circuit. And, I looked at the model parameters for the 240 and 9240 C values: the N has a Cgs off 1457pf and Cgd of 316 and the P had Cgs of 963pf and Cgd 139...
I might guess the single pair circuit is running out of poop due to the loss of Transconductance at almost no Vds (3.5V in my circuit at 20V out). Or it's approching clipping before the lower source resistance of the 4 pair example.

flg 1st September 2008 11:21 PM

Well Lineup, I beleive when you try to drive a follower, the Vgs is actually almost no difference with signal. Because the Source follows, the Gate, there is very little difference Gate to Source, hence, very little capacitance is actually being driven . This is somewhat dependant on gain :xeye: There will be a larger diffrence in Gate to Source voltage with lower gain devices :D
The Gate to Drain voltage though, does see a large change with signal and you are driving it like a capacitor plus some other effects ;)
So, without going into deep math, might N.P. straiten me out :xeye: Or maybe there is a Thumbnail calculation ???

Nelson Pass 2nd September 2008 01:47 AM


Originally posted by flg
Thumbnail calculation ???
For Cgs, these figures are for apparent capacitance, not the
actual capacitance.

If the total input capacitance looks like 75 pf and the Cgd comes
in at 45 pF, then the apparent Cgs thumbnails at 30 pF

Into 4 ohms, it will thumbnail at 60 pF.

Into 0 ohms I believe it will come in around 500-600 pF, on the
order of half its rated Cgs.


EUVL 2nd September 2008 01:53 AM

> Would I then not get close to 135p with a single pair, give or take 20% ?

Perhaps you would care to comment on my reasoning in Post #4 and point out where my thinking might be wrong ?


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