Some other Source Follower Configurations

Just posted this over in the analog line level section. But it may be better placed here, so apologies for the cross post.

I built the Taylor CS follower like the attached and it works nicely. The base of the transistor is a good point to attach a servo although it really doesn't need one. Adding R6 takes away some heat from Q1 so DC doesn't drift so long while the transistor heats up.
 

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Congratulations for your successful build. :)

As already mentioned in #496, there is little advantage of a TCS follower for line level.
Using 2 pairs NJFET in parallel would achieve pretty much the same performance.
There might be a slight advantage for the TCS when RL < 1k.
For typical 10k load, dual FET is actually better.

One need to consider some other things, such as DC stability.
A simple source follower will track pretty well when thermally coupled.
A TCS will actually drift more than a single driver JFET (e.g. loaded by a stabilised CCS).
As it should be, since it senses an increase in driving current and reduce the CCS loading current as so wanted.
Of course one can add DC servo, etc.
But it then gets complicated and no longer so elegant.

Nevertheless, still interesting as experiments and as exercise to understand circuits.
Practically I would just use a simple JFET follower for line level loads personally.

The DAO TCS is a different story, but it is supposed to drive 16 ohm with ease.
Using dual FETs in parallel there means 500mA bias, instead of 250mA with TCS.


Patrick
 
The upper FET has a zero Vgsr nominal.
The lower FET in the TCS has a higher source resistor and needs a positive Vgsr.
i.e. the upper and lower legs are not identical.

This positive Vgsr is generated by the TCS which measures and amplifies the voltage across the current sensing resistor.
So a positive change in the Id of the top FET will cause a negative change in Id of the lower FET, thus magnifying any DC offset.
(Else it cannot be push-pull.)


Patrick
 
But then it will just sit there?

If I tune the base of Q1 such that output DC is zero, Vgs will be the same in top and bottom JFET as both halves are identical resistor and JFET cascode in series = same Id, same Vds, i.e. same Vgs, provided their temperatures are the same and the jfets are matched.

If the JFETS stay at the same temperature (no matter how hot) output DC should stay where it was, shouldn't it?

Edit: there is a difference between top and bottom: the emitter current into Q1. So, more drift.
 
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