Attentuator after the B1
Hello,
in my application I need an attentuator after the B1 (I use the ZM'ed version as buffer after a line-level crossover). Now I see two possibilities: using a 5k attentuator or something higher (100k e.g.) with an extra B1 afterwards.
From the point of parts-count, I would prefer the first approach, but I see some issues with impedance-matching.
What would you recommend?
Thanks in advance
Flo
Hello,
in my application I need an attentuator after the B1 (I use the ZM'ed version as buffer after a line-level crossover). Now I see two possibilities: using a 5k attentuator or something higher (100k e.g.) with an extra B1 afterwards.
From the point of parts-count, I would prefer the first approach, but I see some issues with impedance-matching.
What would you recommend?
Thanks in advance
Flo
Technically you will be better off with 2 buffers. Have done so with op amps in the past. Best for interfacing if you have high Z before the pot and low Z to drive. IMHO better go technically correct first, and as for transparency, at least the double B1s will be the simplest there is to make.
Do my dual PSU no coupling cap stuff so to lose some signal passing parts since you will be adding some jfets. So you may still be at OK transparency levels in the end. Not to mention the 8 quality film caps expenditure skipped.
Do my dual PSU no coupling cap stuff so to lose some signal passing parts since you will be adding some jfets. So you may still be at OK transparency levels in the end. Not to mention the 8 quality film caps expenditure skipped.
Thanks for the answer salas,
I am using the version with symmetric psu and no coupling caps. In the end I will need a cap after the whole thing because even if the dc-offset of one b1 is really low, with several b1 in the signal chain all these offsets add up to a little more then 10mV and I think that's too much.
Best regards
Flo
I am using the version with symmetric psu and no coupling caps. In the end I will need a cap after the whole thing because even if the dc-offset of one b1 is really low, with several b1 in the signal chain all these offsets add up to a little more then 10mV and I think that's too much.
Best regards
Flo
Nelson Pass said:
This is interesting and deserves more discussion. My take is that the distortion is a function of input level, frequency, and source impedance at the JFET gate. For a given fixed source impedance, the nonlinear input capacitance distortion gets worse as input level and/or frequency increase.
So if you use the buffer without a volume pot in front, say in a filter, the resistor to ground is can be very large with no ill effects. But you still need to keep an eye on the source impedance from the preceding circuit.
Also, that with a volume pot, the effect is greatest when the pot is fully counterclockwise, i.e. very low volume. At low volume you have almost the full resistance of the pot in series with the JFET input. This would also be a very low input level, so the two effects would cancel out to some degree.
And, when fully clockwise (full volume), the source impedance contribution from the pot would be zero (for the highest input levels).
So if you choose large pot, and you can frequently listen with it fully clockwise (wide open
), you should not be introducing any extra distortion in that position. I hope I got this right, as I never really thought about it much before. Here's an interesting article that actually shows the same effect for JFET input op-amp, with distortion curves vs. source resistance.
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1008,C1148,P1356,D4280
Bob
no.BFNY said:
With the volume pot at minimum, the source impedance seen by the buffer input is near zero ohms.
With the pot at maximum, the source impedance seen by the buffer input is potvalue// Rs of the source before the pot.
With the pot at -6dB, the source impedance seen by the buffer input is [Rs+Pot value] / 4
using a 50k pot and Rs=200r the source impedance varies between zero ohms and 12k55.
AndrewT said:
OK, agreed, thanks. Need more coffee (had theses courses 30+ years ago, but no excuses).
Here's saying it another way then - if R1 = resistance above pot wiper, and R2 = resistance below wiper, Rth (Thevenin equivelent R) = R1 x R2 / R1+R2
If you assume source output impedance = 0 (or close it it), and JFET input impedance = infinity (or close to it), then the pot output impedance is lowest for cases where the pot is at min AND max values (full CCW AND full CW). In reality, at full CCW it = 0, at full CW = upstream source impedance (provided it is say, 100 times less than the pot value).
And MAX pot output impedance is the setting where wiper R1=R2, where output impedance = pot value/4. This also is the point where Vout = 0.5 Vin, or expressed in dB, -6dB.
If there is time, I'll measure the effect of source impedance on distortion for this circuit and post results. Also some data on using the el cheapo 2n5459. I intend to do this anyways for use in buffering a passive filter application.
I'm afraid that this is one of those situations that has Something-Is-Wrong written all over it. Given that I/we can't lay hands on or hear your system, I think your best bet is going to be finding someone savvy in your area who can actually come over and physically prod the thing. Failing that, your options narrow to giving up (distasteful and wasteful) or taking a break, then coming back to it with fresh eyes to see what's wrong. If you treat it as a learning experience, you can get a lot out of a crash course in troubleshooting a piece of equipment.
People have suggested numerous things to check (granted, some of it contradictory, but unfortunately that's the nature of the web) and that's a starting point. Another possibility that may or may not have been suggested yet (I haven't kept close tabs on this thread) is to get a good book like The Art of Electronics by Horowitz & Hill and read a few chapters to see if it gives you some ideas.
Good luck.
Grey
People have suggested numerous things to check (granted, some of it contradictory, but unfortunately that's the nature of the web) and that's a starting point. Another possibility that may or may not have been suggested yet (I haven't kept close tabs on this thread) is to get a good book like The Art of Electronics by Horowitz & Hill and read a few chapters to see if it gives you some ideas.
Good luck.
Grey
As far as I see on your pics, the outer ring of the chinch connectors isn't connected anywhere. Wire the whole thing like I told you above.
O.k. some basics:
Always think of the fact, that voltage is defined as a DIFFERENCE of the electric potential between TWO points. That means you always have to connect two wires! A single wire has no voltage, it carries no signal. Because the voltage always means a difference, no absolute value, it is necessary to refer the two differences (the voltage of the powersupply and the voltage of the signal) to one "zero". This is done via the connection at the star ground.
With those connections to the ground you have to be careful: if you build a loop, you might get hum.
regards
Flo
O.k. some basics:
Always think of the fact, that voltage is defined as a DIFFERENCE of the electric potential between TWO points. That means you always have to connect two wires! A single wire has no voltage, it carries no signal. Because the voltage always means a difference, no absolute value, it is necessary to refer the two differences (the voltage of the powersupply and the voltage of the signal) to one "zero". This is done via the connection at the star ground.
With those connections to the ground you have to be careful: if you build a loop, you might get hum.
regards
Flo
)
brutepuppy said:
They arrived this afternoon. Tomorrow I'll admire them, and the day after I'll start
stuffing them, and the day after I'll be listening to them, and the day after I'll release
the artwork to the webmaster, and the day after he'll put it up and then you can either
make your own off the gerber files or buy them at the cost of our vendor's invoice
divided by the number of boards plus shipping and fees from financial transaction
agents.