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Old 13th September 2008, 03:20 PM   #621
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They are still on order. Should be in any time.
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Old 13th September 2008, 03:20 PM   #622
Derekva is offline Derekva  United States
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Quote:
Originally posted by Nelson Pass
They are still on order. Should be in any time.
Thank you for the update!
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Old 14th September 2008, 12:03 AM   #623
Floric is offline Floric  Europe
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Default Attentuator after the B1

Hello,

in my application I need an attentuator after the B1 (I use the ZM'ed version as buffer after a line-level crossover). Now I see two possibilities: using a 5k attentuator or something higher (100k e.g.) with an extra B1 afterwards.

From the point of parts-count, I would prefer the first approach, but I see some issues with impedance-matching.

What would you recommend?

Thanks in advance

Flo
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Old 14th September 2008, 12:35 AM   #624
Salas is online now Salas  Greece
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Technically you will be better off with 2 buffers. Have done so with op amps in the past. Best for interfacing if you have high Z before the pot and low Z to drive. IMHO better go technically correct first, and as for transparency, at least the double B1s will be the simplest there is to make.
Do my dual PSU no coupling cap stuff so to lose some signal passing parts since you will be adding some jfets. So you may still be at OK transparency levels in the end. Not to mention the 8 quality film caps expenditure skipped.
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Old 14th September 2008, 11:20 AM   #625
Floric is offline Floric  Europe
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Thanks for the answer salas,

I am using the version with symmetric psu and no coupling caps. In the end I will need a cap after the whole thing because even if the dc-offset of one b1 is really low, with several b1 in the signal chain all these offsets add up to a little more then 10mV and I think that's too much.

Best regards

Flo
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Old 14th September 2008, 01:12 PM   #626
Salas is online now Salas  Greece
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Better safe than sorry.
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Old 14th September 2008, 02:08 PM   #627
Floric is offline Floric  Europe
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Jepp!
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Old 17th September 2008, 01:43 PM   #628
AndrewT is online now AndrewT  Scotland
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yes, it sets the input impedance.
But, a suitable value of Zin is determined by the ability of the source to drive that impedance quietly.
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Old 18th September 2008, 02:18 PM   #629
BFNY is offline BFNY  United States
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Quote:
Originally posted by Nelson Pass


There is a small and nonlinear input capacitance to the JFET, so the
best performance is obtained with values at 50K or below. You can
use 100K if you really have a need.
This is interesting and deserves more discussion. My take is that the distortion is a function of input level, frequency, and source impedance at the JFET gate. For a given fixed source impedance, the nonlinear input capacitance distortion gets worse as input level and/or frequency increase.
So if you use the buffer without a volume pot in front, say in a filter, the resistor to ground is can be very large with no ill effects. But you still need to keep an eye on the source impedance from the preceding circuit.
Also, that with a volume pot, the effect is greatest when the pot is fully counterclockwise, i.e. very low volume. At low volume you have almost the full resistance of the pot in series with the JFET input. This would also be a very low input level, so the two effects would cancel out to some degree.
And, when fully clockwise (full volume), the source impedance contribution from the pot would be zero (for the highest input levels).
So if you choose large pot, and you can frequently listen with it fully clockwise (wide open :-)), you should not be introducing any extra distortion in that position. I hope I got this right, as I never really thought about it much before.

Here's an interesting article that actually shows the same effect for JFET input op-amp, with distortion curves vs. source resistance.

http://www.linear.com/pc/downloadDoc...48,P1356,D4280


Bob
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Old 18th September 2008, 02:53 PM   #630
AndrewT is online now AndrewT  Scotland
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Quote:
Originally posted by BFNY
with a volume pot, the effect is greatest when the pot is fully counterclockwise, i.e. very low volume. At low volume you have almost the full resistance of the pot in series with the JFET input. This would also be a very low input level, so the two effects would cancel out to some degree.
And, when fully clockwise (full volume), the source impedance contribution from the pot would be zero (for the highest input levels).
no.
With the volume pot at minimum, the source impedance seen by the buffer input is near zero ohms.
With the pot at maximum, the source impedance seen by the buffer input is potvalue// Rs of the source before the pot.
With the pot at -6dB, the source impedance seen by the buffer input is [Rs+Pot value] / 4
using a 50k pot and Rs=200r the source impedance varies between zero ohms and 12k55.
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