F5 power amplifier

The intrinsic square-law characteristics of the JFETs and MOSFETs cause nearly all of the distortions. Proper adjustment of P3 can reduce even order distortions to nearly zero. Increasing the bias currents helps, but increases idle power dissipation. Nothing much can be done to reduce odd order distortions other than increasing the amount of negative feedback, at the cost of increasing distortions at higher orders.

Could you tell me what the intrinsic square-law is or give me a link where I can learn about it?

It sounds like only the active devices contribute to the distortion of the amp. Are there other jfet/mosfets that we might want to consider for the F5 that might not have perviously been considered?
 
So if we make the solving a bit more complicated, we could say - instead of nulling second harmonics al together - for example set that at 10 dB higher than 3rd harmonics (which is a given and can be calculated, given the measures characteristics of the devices).
The picture below shows what I think happens, this picture is from a differential pair by the way (Héphaïstos, in L'Audiophile 2/1988).
View attachment 270412
With P3 we also move the operating point a bit up or down, and are content with the trifle of added second harmonics (as long as they are in phase, being natural).

albert

by the way, I did try to lower high frequency gain for a high roll-off, by adding capacitance across the feedback resistors R5-R8, even 2 nF matched to about 2% was not good enough and gave damped ringing (way above 100kHz), so at the end I left the bandwidth all open myself, and that sounded best.

I now see a simpler and more general way to express the problem. The exact Vout(Vin) function for the JFET+MOSFET chain can be a Taylor series expansion of the full equations, resulting in polynomials:

P(x) = sum(i, c*x^i)

The output from pair of amplifier chains with feedback is then:

Vout = P1((1-a1*Gain)*Vin - Vt1) - P2((1-a2*Gain)*Vin - Vt2)

The harmonic analysis in now done in the Fourier domain. For a given input Vin(f) at frequency f, the output response at frequency i*f is c*Vin(f). This approach allows the use of complex coefficients, representing phase information (and capacitors and inductors).

I haven't completed the details, but I expect the response for i-th harmonic something like:

Vin^i * (c1*((1-a1*Gain)) + (-1)^i * c2((1-a2*Gain))


Another interesting discovery:

Source resistor degeneration is known to be a type of local negative feedback. I have equations that show that source degeneration introduces higher order harmonic distortions in proportion to the amount of local feedback. This suggests higher harmonics might be reduced by reducing source degeneration. Unfortunately, that increases the open-loop gain, which increases either the amplifier Gain or the global feedback.
 
Start an F5 theory thread?

I am mystified now . . . we try to maximize 2nd harmonics of the right phase, don't we? (see my avatar . . that shows a tube output).
...
Can you also find that point in the math, that would be cool.
albert


All of you who are interested in circuit theory as applied to the F5 (and related amplifiers) I suggest we start a new thread. I am very interested in thoroughly understanding why the F5 can be adjusted to work so well.
 
by the way, I did try to lower high frequency gain for a high roll-off, by adding capacitance across the feedback resistors R5-R8, even 2 nF matched to about 2% was not good enough and gave damped ringing (way above 100kHz), so at the end I left the bandwidth all open myself, and that sounded best.


In the F5-Turbo paper, Nelson suggested adding caps between the output
and the MOSFET gates, rather than across the feedback resistors. In Spice simulations I found that I could greatly reduce the 20KHz harmonic distortion by adding about 500pf from the output to gate of the P-channel MOSFET, an IRFP9240 in my case. 500pf is the right amount to equal the balance the gate-drain capacitances of the 2 MOSFETs.

The overall frequency response is still peaks by about .15dB at 360kHz. This was cured by adding 200pf from the JFET gates to ground.

This looks much more promising than caps across the feedback resistors.
 
If you had 2 pairs of caps, two 68kuf and 33kuf, and you wanted to use the in an f5 power supply, which would you have closer to the amp board and which would be closer to the rectifier? Does it even matter?

The smaller one against the rectifier. This reduces the inrush current. It is the inrush that upsets even the biggest rectifier blocks (thermal/reverse) and transformers (saturation effects). I choose even smaller up front one that still can handle 10 amp ripple.
 
The smaller one against the rectifier. This reduces the inrush current. It is the inrush that upsets even the biggest rectifier blocks (thermal/reverse) and transformers (saturation effects). I choose even smaller up front one that still can handle 10 amp ripple.

Thanks, I have it the other way around and I think it might be causing some small problems.
 
- - -In Spice simulations I found that I could greatly reduce the 20KHz harmonic distortion by adding about 500pf from the output to gate of the P-channel MOSFET, an IRFP9240 in my case. 500pf is the right amount to equal the balance the gate-drain capacitances of the 2 MOSFETs.
This is a god idea [I should do too]; it is because the input capacitances of tewo P-FETS and two N-FETS differ.
One extra trick: connect the 500 pF not to ground but to the source resistor of the P-FET. That way the static value is reduced just like the gate-source resistance dynamically on the N-side.

The overall frequency response is still peaks by about .15dB at 360kHz. This was cured by adding 200pf from the JFET gates to ground.

This looks much more promising than caps across the feedback resistors.

I am still curious as to how the .15 dB level shift occurs; in my implementation I remember it stays rather over a broad frequency range (that is why I call it a shift). So if this also occurs with the IRFP[9]240 . . it is not due to my Toshiba's and my air-wiring to my dislocated TO-3 devices.