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Old 13th July 2009, 01:09 PM   #4501
AndrewT is offline AndrewT  Scotland
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take a first assumption that the operating Vgs is 500mV.
That leaves ~24.1V across the Vr=3870.
Is~6.2mA.
Look up the test data or graph for the actual Vgs of the chosen jfet Idss=XYmA and read off the Vds.
Recalculate the Vr current and you are there.

For the circuit as shown I would select an Idss ~8mA
But, that high Vdg~25V worries me.

edit.
should Vvr be 24.6-(-0.5)=25.1V?
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Old 13th July 2009, 01:09 PM   #4502
pro is offline pro  Italy
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Bobo, the source is at Vgs given from 6.4 mA on R1.

Andrew, i'm simuleting the F5 front end for choose to fet the closest possible in Vgs for N and P channel, because with those I have now, choosen casually, I have one trimmer (on the J74) that is to much sensible to the regulation, whili the other is less sensible, so easy to regulate, and the bias chosen from NP in the F5 project is 6mA.
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Old 15th July 2009, 03:44 PM   #4503
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Quote:
that is to much sensible to the regulation
According to Nelson's recommendations, it is not necessary to match jfets.
I have built two amps without matching neither problem.
May be it will behave a little differently when using thermistors and biasing @1,3A.
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Old 16th July 2009, 07:27 AM   #4504
lalaina is offline lalaina  Madagascar
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hi to all,

I have made some mesure of the out of my new build F5.

I can't obtain a square as stable as in the service manual

Click the image to open in full size.

square wave

Click the image to open in full size.

square wave


Click the image to open in full size.


power noise ( in the capacitor filter)



may be, I have a grounding problem ? or the amplifier is too fast ? 160ns of rise time

test made with 8 ohm resistive load

or the amplifier sound great.

biased at 1.34A and 3mv of outpu offset.

Excuse-me for my poor english.

regards

lalaina
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Old 16th July 2009, 08:17 AM   #4505
Mooly is offline Mooly  United Kingdom
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Your top trace looks like a bit like an inductive component ringing. Output inductor ? It could be also be down to grounding, the input ground being contaminated in some way.
The middle trace is of more concern, there appears to be some oscillation occuring. Connect your scope probe tip and ground together... should be perfectly clean trace... now keeping them shorted touch the amp ground. Does the scope trace "thicken" and show that HF oscillation. If so try a low value (100 ohm say) in the scope ground lead.
Remember that absolutely nothing in audio will approach those rise times... I know that's another argument, we won't go there
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Old 16th July 2009, 02:23 PM   #4506
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looks like some oscillation which I am guessing -- but perhaps 3MHz? Just about the f3 frequency of the gate stopper and input capacitance of the MOSFET.

You can experiment with the value of the gatestopper. As the value increases the f3 is lowered, but too high a value and the amp will break into oscillation. I've used different values of gatestoppers on N and P channel devices.

On the boards which I burned for myself I have a very short run both from gate-stopper to the MOSFET, and from JFET drain to gate-stopper. I've also used everything from Ohmite TWW5, Mills, Jaro's and Dales as the 0.47R/3W resistor and haven't seen this as a source of that type of oscillation.

Can you demonstrate for us a 20kHz sine wave so we can look at the top and bottoms?
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Old 16th July 2009, 03:32 PM   #4507
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Hi Lalaina,
Is your F5 boxed now?
Could you show a picture of the wiring?


From the PDF manual:
..."A caveat is in order here – this is a very wide band amplifier with a high input impedance. In order to prevent the output voltage from bleeding back to the input at very high frequencies (thus making a i ne power oscillator), keep the input and output cables separate, and don’t externally connect the speaker ground to the input ground. Good ground shielding on the
input cables is important, and caution is called for in using Litz and other specially low inductance / high capacitance cables." ...
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Old 16th July 2009, 04:31 PM   #4508
Renron is offline Renron  United States
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Quote:
Originally posted by massimo
To get the max efficiency, one should fix the two mosfet exactly at the center of each heatsink. That means about 200 mm apart and at 82 mm high

Massimo,
I have read that the heat source (mosfet) should be placed at 1/3 up from the bottom, not centered vertically. (heat rises through convection)
Horizontally, yes. But vertically no.

Ron
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Old 16th July 2009, 04:35 PM   #4509
tinitus is offline tinitus  Europe
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I would presume that too
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Old 16th July 2009, 05:54 PM   #4510
sangram is offline sangram  India
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I'm sorry if I missed this in the 180-page thread, but are there any reliable substitutes in the Digikey catalog for the input pair J108/K170? I can't seem to find those FETs anywhere, but D-K has quite a few complementary (matched??) pair FETs in SOIC-8 packages. And they are reasonably cheap, around 3 dollars each.

I assume there's a catch there somewhere, or could I just pick one of those with the right voltage and current ratings? Or is there more to it? I'll be using perfboard and SOIC->DIP adapters to mount them.

There's another thread around here about getting the same FETs for the F4, and it turned up the k370/J74, and those are not on D-K either. I basically want to save on shipping costs, so would prefer to get everything from a single source if possible.

Thanks for the assistance
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