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Old 8th March 2012, 09:58 AM   #11971
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Quote:
Originally Posted by lhquam View Post
All of you who are interested in circuit theory as applied to the F5 (and related amplifiers) I suggest we start a new thread. I am very interested in thoroughly understanding why the F5 can be adjusted to work so well.
do post the link here though.
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Old 8th March 2012, 02:26 PM   #11972
lhquam is offline lhquam  United States
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Quote:
Originally Posted by jacco vermeulen View Post
You need equations for that ?
I find equations helpful for understanding the phenomenon. In particular, how else can you really understand the distortion cancellations that take place in the F5 push-pull pair or in SUSY amplifiers?
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Old 9th March 2012, 10:38 PM   #11973
lhquam is offline lhquam  United States
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Quote:
Originally Posted by triode_al View Post
by the way, I did try to lower high frequency gain for a high roll-off, by adding capacitance across the feedback resistors R5-R8, even 2 nF matched to about 2% was not good enough and gave damped ringing (way above 100kHz), so at the end I left the bandwidth all open myself, and that sounded best.

In the F5-Turbo paper, Nelson suggested adding caps between the output
and the MOSFET gates, rather than across the feedback resistors. In Spice simulations I found that I could greatly reduce the 20KHz harmonic distortion by adding about 500pf from the output to gate of the P-channel MOSFET, an IRFP9240 in my case. 500pf is the right amount to equal the balance the gate-drain capacitances of the 2 MOSFETs.

The overall frequency response is still peaks by about .15dB at 360kHz. This was cured by adding 200pf from the JFET gates to ground.

This looks much more promising than caps across the feedback resistors.
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Old 10th March 2012, 04:51 AM   #11974
JZatopa is offline JZatopa  United States
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If you had 2 pairs of caps, two 68kuf and 33kuf, and you wanted to use the in an f5 power supply, which would you have closer to the amp board and which would be closer to the rectifier? Does it even matter?
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Old 10th March 2012, 08:56 AM   #11975
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Quote:
Originally Posted by DJNUBZ View Post
If you had 2 pairs of caps, two 68kuf and 33kuf, and you wanted to use the in an f5 power supply, which would you have closer to the amp board and which would be closer to the rectifier? Does it even matter?
The smaller one against the rectifier. This reduces the inrush current. It is the inrush that upsets even the biggest rectifier blocks (thermal/reverse) and transformers (saturation effects). I choose even smaller up front one that still can handle 10 amp ripple.
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Old 10th March 2012, 02:43 PM   #11976
JZatopa is offline JZatopa  United States
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Quote:
Originally Posted by triode_al View Post
The smaller one against the rectifier. This reduces the inrush current. It is the inrush that upsets even the biggest rectifier blocks (thermal/reverse) and transformers (saturation effects). I choose even smaller up front one that still can handle 10 amp ripple.
Thanks, I have it the other way around and I think it might be causing some small problems.
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Old 11th March 2012, 01:57 PM   #11977
eyoung is offline eyoung  United States
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I have another P/S question using an Antek 4218 400VA transformer I have some dual diode 600V 100A ultra fast soft recovery , should I snubber and if so caps only or cap and resistor/ what values?

regards,E
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Old 11th March 2012, 01:59 PM   #11978
AndrewT is offline AndrewT  Scotland
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Check the PSU rail for ripples and for damped oscillations. Then decide if a snubber/s is needed.
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Old 11th March 2012, 02:45 PM   #11979
eyoung is offline eyoung  United States
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Thanks Andrew. I need to get up off my duff and start soldering

Regards, E
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Old 11th March 2012, 04:22 PM   #11980
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Quote:
Originally Posted by lhquam View Post
- - -In Spice simulations I found that I could greatly reduce the 20KHz harmonic distortion by adding about 500pf from the output to gate of the P-channel MOSFET, an IRFP9240 in my case. 500pf is the right amount to equal the balance the gate-drain capacitances of the 2 MOSFETs.
This is a god idea [I should do too]; it is because the input capacitances of tewo P-FETS and two N-FETS differ.
One extra trick: connect the 500 pF not to ground but to the source resistor of the P-FET. That way the static value is reduced just like the gate-source resistance dynamically on the N-side.

Quote:
The overall frequency response is still peaks by about .15dB at 360kHz. This was cured by adding 200pf from the JFET gates to ground.

This looks much more promising than caps across the feedback resistors.
I am still curious as to how the .15 dB level shift occurs; in my implementation I remember it stays rather over a broad frequency range (that is why I call it a shift). So if this also occurs with the IRFP[9]240 . . it is not due to my Toshiba's and my air-wiring to my dislocated TO-3 devices.
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