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Old 30th September 2008, 06:28 AM   #201
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After some hacking I've piggybacked some serious reclocking onto the D1V3.

The setup basically consists of a PIC microprocessor performing phase detection and driving a 16bit LT industrial DAC which in turn controls the Tent Labs VCXO. The VCXO output drives the Tent/AudioDAC schema which clocks the DF, PCM63's and reclocks LE and DATA lines.

It's a bit of a messy construction with strip board adapters carrying the reclocker 74HC175's plugged in to the sockets which previously held the 74HC86 XOR gates.

The PIC PLL has turned out to be fantastic, and is easily achieving sub-1hz update rates (effectively the same as loop filter frequency) on the VCXO. The PLL doesn't actually switch to a low gain setting until the VCXO update rate is below 0.7hz and then drifts in a loose lock against the incoming clock within the range allowed by the SM5842 jitter free mode.

Overall the in this configuration dac sounds vastly improved over the D1V3 with my implementation of the D1 PLL/VCXO. Better detail, imaging, bass extention and definition.

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Old 2nd October 2008, 08:37 PM   #202
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Default Bypass CAPS to Radj on the LM337/317 reg

Hello!
I ask gently to spzzzzkt (and to all who have done this mod) how to fit the Bypass CAPS to Radj on the LM337/317 regulators on the PCB?
Can you post a photo?
Thanks a lot. Sincerely.
Davide.
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Old 12th October 2008, 12:28 PM   #203
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Default Bypass CAPS to Radj on the LM337/317 regulators

Hello!
I am trying to apply the mod made by spzzzzkt (to put the Bypass CAPS to Radj on the LM337/317 regulators on the PCB).
What is the Voltage recommended for this CAPS?
Thanks a lot. Sincerely.
Davide.
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Old 12th October 2008, 09:39 PM   #204
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I haven't actually added the caps at this stage. The mods I've done to the regs were to replace the adjust resistors with parallel zener diodes, but even so the caps should still have a positive effect.

You won't see much more than (output voltage - 1.25V) across the lower adjust resistor, so even 6.3V would work. However the aim is to get a cap with low impedance to maximise the benefit. Something like 100 or 120uF/35V Panasonic FM or Rubycon ZA would be ideal. If you can get your hands on some 56uf/25V OSCON SP's they have close to half the impedance of the FM or ZA's.

Martin Clark's page is probably the best DIY reference on 3*7 tweaking:

http://www.acoustica.org.uk/t/3pin_reg_notes1.html

cheers
Paul
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Old 13th October 2008, 07:06 AM   #205
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Hello Paul,
many thanks for your your help and for your patience.
I have found some of the following CAPS

SANYO Ultra Low ESR
[Series] SANYO OS-CON SP Series [Rating] 100uF/16V
[Dielectric] ALUMINUM Electrolytic Capacitor for Audio
[Physical size] D:10mm * H: 5mm
[Pitch] 5mm

Do you think they could work fine in that application?
Thanks again. Best regards.
Davide.
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Old 13th October 2008, 11:18 AM   #206
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The 16V/100uF SP's have the same ESR as the 25V/56uF SP's so there would be no real difference in performance between the two.

The trade off is getting a cap which is small enough to mount comfortably and which has low ESR - and the OSCONs look like a nice balance.
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Old 13th October 2008, 11:21 AM   #207
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The 16V/100uF SP's have the same ESR as the 25V/56uF SP's so there would be no real difference in performance between the two. If you can find the 6.3mm diameter version of the 16V/100uF that would be close to perfect for this task. The skinner case will be easier to mount, and gives slightly shorter lead length.

The trade off is getting a cap which is small enough to mount comfortably and which has low ESR - and the OSCONs look like a nice balance.
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Old 28th October 2008, 07:30 PM   #208
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Default Reclocking-can it be this simple??

Paul,

Quick question on reclocking. I'm not so familiar with the digital side of things and looking at the schematic you've produced, it seems complex, with a 74HC4020 etc floating around.

I thought I could try the following simple approach:

Pin 3 of SM5842 provides the clock for a 74HC74 into which I feed LE, which is then reclocked and then goes via 100R into PCM63. And if using Pin3 as a clock causes metastability issues, maybe inverting the output of Pin 3 on SM5842 will help?

Question is would it work?

Other question is: I have an 11.xxxMHZ canned oscillator from Tentlabs lying around. What is the VCXO you have in your schematic?

http://www.diyaudio.com/forums/attac...amp=1217309476
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Old 28th October 2008, 08:28 PM   #209
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The schematic is an adaptation of the one shown in the D1 service manual. The reason for the 4020 is that the design uses the Fsync output of the CS8412 which gives a clock of 44.1khz (Fs) rather than SCK which outputs 256Fs. The 4020 is configured to divide output of the VCXO by 256 to feed back into the comparator of the PLL.

On Guido Tent's advice I've been looking at other ways of handling the PLL rather than the using 74HC4060, so my current setup uses a PIC micro to perform clock divisions and comparator functions.

Pin 3 on the CS5842 selects whether the internal clock frequency is 256 or 384Fs, so won't work. You could use pin 10 - CKO. The problem with using the Clock output of the DF is that the clock isn't particularly clean so feeding a reclocker from this source isn't going to give an improvement over just directly using the DF outputs. If you use a clean clock to feed the 74HC74 this path is worthwhile, but then you need the "complications" to get it to work.
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Old 29th October 2008, 04:50 AM   #210
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Thanks, would there be a way to clean the CKO clock at all, lets say feed it through a 74hc74 which is using an independant clean clock like a canned oscillator at xxx MHZ?
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