Hello Joschl,
Copper foil is easy to get in shops which sell guitar parts. E.g. http://www.bassparts.de/ in Germany or http://www.allparts.com in USA.
Keyword shielding (Abschirmung)
Best wishes
Copper foil is easy to get in shops which sell guitar parts. E.g. http://www.bassparts.de/ in Germany or http://www.allparts.com in USA.
Keyword shielding (Abschirmung)
Best wishes
Hello,
... just remebered this source for copper foil:
www.stewmac.com
@regal
Mine doesn't oscillate at all without shielding. But I use a different layout and big cylindrical Mundorf caps noramlly used for speaker crossover.
Best wishes
... just remebered this source for copper foil:
www.stewmac.com
@regal
Mine doesn't oscillate at all without shielding. But I use a different layout and big cylindrical Mundorf caps noramlly used for speaker crossover.
Best wishes
Just a note on the jumpers around the DF for those who need to set jitter free mode on a SM5842 or PMD100:
The NORM position selects "Jitter Free" mode, whilst the FREE position selects "Sync Mode"
This probably only makes a difference to those interested in running the D1V3 from an VCXO, as the jitter free mode is required to compensate for slight differences in the clocks. Sync Mode tends to result in soft clicks avery 30 seconds or so in my setup.
The NORM position selects "Jitter Free" mode, whilst the FREE position selects "Sync Mode"
This probably only makes a difference to those interested in running the D1V3 from an VCXO, as the jitter free mode is required to compensate for slight differences in the clocks. Sync Mode tends to result in soft clicks avery 30 seconds or so in my setup.
I did already 
http://www.diyaudio.com/forums/showthread.php?postid=1572298#post1572298
If you take a look at the lower portion of the rev2 pdf it shows an improved version of what I'm currently running. U5, U7, U8, VCXO are the bits you need for feed VCXO output to the DF. The schematic capture software I'm using doesn't give correct part numbers for the chips. They are all 74HC series so, 74HC4046, 74HC4020, etc. The RC filter on the VCXO 5+ supply drops the voltage to +4.6V or so which is a bit too low. I'd recommend replacing the 7805 reg with an LM317 set for 5.5V and use the zener or green led "trick" documented at http://www.acoustica.org.uk/t/3pin_reg_notes1.html to drop the output noise down a couple of notches.
The PLL Bias is optional. I'm undecided about the benefit. It's intended to overcome the deadzone of the 4046, but the bias seems to mean the 4046 is always outputting a pulsed voltage which is probably not ideal. It might be worth putting in a jumper (after R18) so you can test both options.
The rest of the reclocking is lifted from Guido et al's Audio DAC schematic, and is currently untested by me. If you want to play with that it should work, but you'll need to study the original schematics for component values etc.
http://www.diyaudio.com/forums/showthread.php?postid=1572298#post1572298
If you take a look at the lower portion of the rev2 pdf it shows an improved version of what I'm currently running. U5, U7, U8, VCXO are the bits you need for feed VCXO output to the DF. The schematic capture software I'm using doesn't give correct part numbers for the chips. They are all 74HC series so, 74HC4046, 74HC4020, etc. The RC filter on the VCXO 5+ supply drops the voltage to +4.6V or so which is a bit too low. I'd recommend replacing the 7805 reg with an LM317 set for 5.5V and use the zener or green led "trick" documented at http://www.acoustica.org.uk/t/3pin_reg_notes1.html to drop the output noise down a couple of notches.
The PLL Bias is optional. I'm undecided about the benefit. It's intended to overcome the deadzone of the 4046, but the bias seems to mean the 4046 is always outputting a pulsed voltage which is probably not ideal. It might be worth putting in a jumper (after R18) so you can test both options.
The rest of the reclocking is lifted from Guido et al's Audio DAC schematic, and is currently untested by me. If you want to play with that it should work, but you'll need to study the original schematics for component values etc.
Paul,
Just a little note of warning:
A VCXO secondary PLL approach is, by definition, a very "loose" control loop; that is, it follows only slowly and with a certain amount of error the variations in the recovered SPDIF clock. Because of this a temporary buffer is needed for the data stream, for sure. The Tent Dac, for example, takes advantage of the digital filters built in FiFo capability, this was one strong reason why they have chosen the SM5842.
I see You have repeated this setup in your schem. Just wanted to say that not all the digital filters are having this feature already built in, for example the PMD100 do not have this - your scheme will not work with a PMD100. It will regularly mute, when there will be a shift greater than 'tot' value between the two clocks.
With a tighter PLL loop [such as the one in the crystal receivers] this is not a problem, the errors are small [together with the recovered clock quality]
This is a problem what I have encountered when trying the PMD100 in my tent dac.
The solution is: one can use the crystal receiver's similar fifo capability instead; the appropriate mode should be selected, and fsynch should be supplied externally [divided from the VCXO clk] to the common joint between dair-digfilter. In this way one can exchange digital filters with a greater freedom.
Ciao, George
Just a little note of warning:
A VCXO secondary PLL approach is, by definition, a very "loose" control loop; that is, it follows only slowly and with a certain amount of error the variations in the recovered SPDIF clock. Because of this a temporary buffer is needed for the data stream, for sure. The Tent Dac, for example, takes advantage of the digital filters built in FiFo capability, this was one strong reason why they have chosen the SM5842.
I see You have repeated this setup in your schem. Just wanted to say that not all the digital filters are having this feature already built in, for example the PMD100 do not have this - your scheme will not work with a PMD100. It will regularly mute, when there will be a shift greater than 'tot' value between the two clocks.
With a tighter PLL loop [such as the one in the crystal receivers] this is not a problem, the errors are small [together with the recovered clock quality]
This is a problem what I have encountered when trying the PMD100 in my tent dac.
The solution is: one can use the crystal receiver's similar fifo capability instead; the appropriate mode should be selected, and fsynch should be supplied externally [divided from the VCXO clk] to the common joint between dair-digfilter. In this way one can exchange digital filters with a greater freedom.
Ciao, George
George,
Thanks for the correction. I wasn't 100% sure about the PMD-100 - I made the mistake of assuming that it's compatibility with the SM5842 extended to the fifo buffer. I'd briefly tested my existing VCXO setup (same as PLL shown on the schematic less the inverter block) with a PMD100 and hadn't noticed any mute/resync events. The VCXO board has been retired for the D1V3 moment while I work on the DPLL so I can't check easily at the moment.
edit: I think one possible reason our different observations is that the D1 PLL is not nearly as "loose" as the Tent Labs PLL. It locks within a second or so rather than 10's of seconds for the Tent PLL you've mentioned elsewhere. It may be that the D1 PLL is keeping the clocks within the timing limits of the PMD-100. I've also seen comments made by owners of the Pass D1 that the dac is rather sensitive to transport quality, so this would confirm that the vcxo doesn't "float" against the incoming clock to any significant degree.
cheers
Paul
Thanks for the correction. I wasn't 100% sure about the PMD-100 - I made the mistake of assuming that it's compatibility with the SM5842 extended to the fifo buffer. I'd briefly tested my existing VCXO setup (same as PLL shown on the schematic less the inverter block) with a PMD100 and hadn't noticed any mute/resync events. The VCXO board has been retired for the D1V3 moment while I work on the DPLL so I can't check easily at the moment.
edit: I think one possible reason our different observations is that the D1 PLL is not nearly as "loose" as the Tent Labs PLL. It locks within a second or so rather than 10's of seconds for the Tent PLL you've mentioned elsewhere. It may be that the D1 PLL is keeping the clocks within the timing limits of the PMD-100. I've also seen comments made by owners of the Pass D1 that the dac is rather sensitive to transport quality, so this would confirm that the vcxo doesn't "float" against the incoming clock to any significant degree.
cheers
Paul
I had a problem with slight static in one channel of the D1V3, so instead of rebuilding the D1 I/V I decided to add a tube output to the D1. I have a switch that changed the output to tube or SS.
To my surprise I still had static in that channel. It was cured by tieing BPO to Iout. Now every PCM+tube DAC schematic I have seen ties BPO to ground. But when I did this I had significant DC offset on Iout (100 mV.)
What exactly does the BPO output do ?
To my surprise I still had static in that channel. It was cured by tieing BPO to Iout. Now every PCM+tube DAC schematic I have seen ties BPO to ground. But when I did this I had significant DC offset on Iout (100 mV.)
What exactly does the BPO output do ?
You can read this thread:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=97504
... and contact Spencer. Maybe he can help you. He is a nice guy.
http://www.diyaudio.com/forums/showthread.php?s=&threadid=97504
... and contact Spencer. Maybe he can help you. He is a nice guy.
What resistors?
Hello to all!
I usually use for my electronics Xicon MF series or Yageo MFR-25 series. Do you thinks that for this wonderful DAC it is better to use special (and more expensive) resistors made by HI END constructors (as Vishay Dale, Caddock ecc)?
Many thanks. Best regards.
Davide.
Hello to all!
I usually use for my electronics Xicon MF series or Yageo MFR-25 series. Do you thinks that for this wonderful DAC it is better to use special (and more expensive) resistors made by HI END constructors (as Vishay Dale, Caddock ecc)?
Many thanks. Best regards.
Davide.
Hi Davide,
I got email from Spencer, this below is quoted for the resistor matter:
"The resistor quality is not so much important as long as it is 1% metal film type. If you can afford, use all Dale resistors or even better one. Note that most resistor is not improtant to the sonic performance of the DAC as resistor is a very linear device!
You may want to use good resistors for the IV ressitors you mention and also the output current limit resistor R19/20/40/30 (22R) in the signal path. The 22R resistor can be any resistor value from 10 to 33 ohm. Too high will increase the output resistance too much but the resistor should not be below 10 ohm. This is to prevent the out put from short circuit and damage the output Jfets buffer."
and...
after tried some resistors then I agree with him.
Thanks.
I got email from Spencer, this below is quoted for the resistor matter:
"The resistor quality is not so much important as long as it is 1% metal film type. If you can afford, use all Dale resistors or even better one. Note that most resistor is not improtant to the sonic performance of the DAC as resistor is a very linear device!
You may want to use good resistors for the IV ressitors you mention and also the output current limit resistor R19/20/40/30 (22R) in the signal path. The 22R resistor can be any resistor value from 10 to 33 ohm. Too high will increase the output resistance too much but the resistor should not be below 10 ohm. This is to prevent the out put from short circuit and damage the output Jfets buffer."
and...
after tried some resistors then I agree with him.
Thanks.
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