Can anyone confirm if this is the correct output behavior for the D1?
With the attached SIM's see how the vertical alignment of the output voltage swings with the minimum and maximum settings of PL55. PL55 set to minimum seems right, but at maximum the signal voltage decreases slightly, and the +/- waveforms change their vertical alignment.
Somehow this cannot be correct?
-David
With the attached SIM's see how the vertical alignment of the output voltage swings with the minimum and maximum settings of PL55. PL55 set to minimum seems right, but at maximum the signal voltage decreases slightly, and the +/- waveforms change their vertical alignment.
Somehow this cannot be correct?
-David
Attachments
Oh, I see!
I'm not sure, but it kinda looks like it is implemented differently on your schem compared to the service manual.
In the service manual, I supose the "volume+" of PL55 is connected to "vol+" of the IV diagram, and if this is correct, the capacitor C1 is just left dangling in parallel with the resistors until the wiper. In this way, unlike your schem, the capacitor is not placed between the active nodes.
It does however seem a bit odd to me, but it might be worth a try in the simulator.
I'm not sure, but it kinda looks like it is implemented differently on your schem compared to the service manual.
In the service manual, I supose the "volume+" of PL55 is connected to "vol+" of the IV diagram, and if this is correct, the capacitor C1 is just left dangling in parallel with the resistors until the wiper. In this way, unlike your schem, the capacitor is not placed between the active nodes.
It does however seem a bit odd to me, but it might be worth a try in the simulator.
cviller said:Cool. Then you just have to replace the irf610 with jfets as papa always suggests...
Yup agree!! I just got a nice handful of LSK389's in the mail yesterday. It helped me to understand the original I/V as a starting point.
Thank you again cviller.
-David
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