differencial operation question

[bobsinclar]

Hello,
I am building a preamp based on the classic differencial topology,
which consist in 2 cascoded fets, bisased by a current source (fet),
I use the negative input grounded and inject the signal in the +input, the 2 gain devices are coupled to each other with 400Ohm resistor (at their source pins), and my quiestion to those who are familiar with these types of preamps, like Balances Bride of SOZ, are the 2 signals coming out from the preamp supposed to be the same exact voltage level swing when using only one input?
as for me the only way I can get 2 identical signals at the + and - outs is to replace the coupling resistor with a piece of wire, but that way the gain climbs much too high...
should I live with that ? I mean keeping a coupling resistor but also keeping 2 signals balanced with one having a bit less level than the other?
many thanks for your help!
Vince

[CheffDeGaar]

Hi Vince,

Care posting a schematic ?

From your post, I can not see whether you're using one or two current sources... Hard to see how you connected one current source using a source-to-source resistor. If you use only one CCS, you should consider splitting your 400R resistor into two identical Rs, and feeding the current source at the junction of the two R's.

If you adopted the source-to-source gain resistor, you should use two current sources, each one being attached to the source of a JFet. The drawback is the use of two CCS, and the advantage is the gain setting by only one resistor, and making the gain variable is much easier here than varying two source degeneration resistors equally...

For illustration :
Two CCS, one gain res :
http://www.diyaudio.com/forums/showt...920#post322920

One CCS, two res :
http://www.diyaudio.com/forums/showt...29#post1159229

Hope this helps

[GRollins]

Like Cheff, I'm not entirely clear about what you're describing.
I'm also not sure I understand why it matters if the two sides' signals are asymmetrical if you're only using one output.
That said, I'll toss a few random things into the pot:
--A differential with sufficient impedance under its tail will provide equal signals at the two outputs. This assumes that the differential itself is symmetrical. If you've used a resistor under the Source of one JFET but not under the other, then naturally the signals will be asymmetrical, too.
--If you feel that you have too much gain, you can always reduce it by using smaller load resistors on the differential.
--Another possibility is to use a pot or resistive divider for the load and set the gain to whatever level you wish.

Grey

[bobsinclar]

Hello Cheff and Grey,
many thanks for your inputs, Here I posted the actual schematic, I hope you will take a short look at it and maybe it will help you understand better what I was worried about...
actually I used only one CCS for the diff pair... but in my first schematics I used 2 CCS(resistors) and coupled them with a resistor...but the problem was the same...

actually I need the 2 outputs because I will drive my Aleph 30 that is balanced, but as my CD player has asymetrical output, I wanted to use only the + in (this is why i grounded the other leg)
and the problem is that signal at the output is well inverted, but presents a small, but noticeable attenuation when considering the negative output...
considering this schematic should I expect to have the same exact swing voltage coming out from the 2 outputs?
many thanks for your time and help!
Vince

[GRollins]

Those voltages can't be right. Amongst other things, an IRF610 (e.g. the current source) subjected to 82V of Vgs is going to be one unhappy customer.
Is the voltage at the Drains of both cascodes the same?
Why do you have both 200 Ohms and 39 Ohms per 2SK170?

Grey

EDIT: Just noticed the diode at the Gate of the current source, which may explain the enormous voltage...am I to assume that it's a Zener?

Second EDIT: You kinda left out the part about running three 2SK170 in parallel...that increases your transconductance considerably, which means more gain, which in turn you're trying to burn off at the Sources. Um...just shooting from the hip here, I'd say you might want to start with a clean sheet of paper and a much lower rail voltage. You certainly aren't under any obligation to do this the way I'd do it, but it could be considerably simplified.

[bobsinclar]

Hi Grey,
actually I used the 39Ohm at each Jfet to match them (and because I had no 20Ohm left, I took those 39Ohm...
and the 200Ohm after them was taken arbitrarily...as said I can reduce this value to 0Ohm, but the gain climbs and even the preamp clips...and I remember some of Nelson's amp using this kind of value...before joining the CCS

as for the CCS fet it's gate is at about 11V (due to the zener) sorry about that but i drawed the schematic that quickly, I forgot to mention that it was a 11.5V zener...
so the VGS is about 3.3V...
does this help?

[bobsinclar]

Hi Grey, sure I could consider using only one J fet for each side...
but I tried the unbalanced version of that circuit yet and it sounded quite good, here is just an attempt to make it differencial...just as a sort of tutorial, having 3 J fets also reduces distortion, so it hasn't only drawbacks, this is at least what I thought, but I admit that you are totally right this is objectable to use 3 of them , I was just corious to try that...and see what sound it could give...
so should I get the same signal in size at the 2 outputs? it looks to me that as lond as the j fets are separated by resistors this can explain this loss in the signal?!
sorry to stay straight with this schematic and question Grey, but it's at least important to me to understand what happens, and why the signal isn't perfect match at the output..
Thanks for your help
Vince

[CheffDeGaar]

Hi Vince,

Thanks for the schematics, makes things clearer. Only positive supply, uh ?

First, I think your 3Meg input resistors are far too high, and lowering them to 100K will help a bit imho (and change the 1Meg to 33K accordingly). And I guess dissymetry (is it english ?) problem comes from here : grounding the capacitor on the - input will still let float the corresponding gate, the 3Meg/1Meg resistors being able to catch whatever wanders around here The gate voltage may not be nailed to a fixed value enough to allow proper differential operation considering the small JFet Vgs voltage.

If I read your schematic correctly, you've only got 3V between the source resistors and the drains of the JFets. Far too low Vds. Leave 10/15V for proper operation, and you'll feel better.

I'd change the two cascode voltage pots to only one, far easier to trim.

You do not need to have such a high voltage on the input gates, and lowering it will reduce the CCS single mosfet dissipation. It will translate the burden to the cascode mosfets, but they're two of a kind.

Don't forget to tie your output capacitors to ground through resistors (100K for instance)

To sum up, lower both the gate bias voltage and the resistor values in the divider, allow 10/15V of Vds for the Jfets, use only one cascode bias pot (tie the gates together). If you want to keep the low pass filter on the cascode voltage adjustment, lower the res and increase the cap (high res picks up more noise in this context).

Tell us how it goes

[bobsinclar]

Hey Cheff,
looks like a great bunch of points I have to try! thank you very much for all your precise advises! I will try to put that up this week end!
as a matter of fact the differencial works perfectly now, I had a blown mosfet, and this is why it wasn't symetric...
now I replaced it and it's neat, the 2 outputs have the right same voltage swing
anyway I now will try to experiment all your advises,
you actually are right the 1 and 3Mohm resistors have to be changed...

also I thought using the J fet at low voltage was a good thing, according to Nelson's ZV9 he played the J fet around 3Volt Vds, I thought it was an improvment...isn't it with this specific device?
Thanks for your help!
Vince

[CheffDeGaar]

Hi Vince,
Pas couché ?

Glad you had it working
Maybe I wrote to quickly, forgetting the cascode Sorry for that. You're operating the Jfets @ a pretty high current (8.5mA/each from your schematic), and dissipation may be an issue if you allow 15V for Vds. Cascoding helps reducing the adverse effects of the Id dependence of Vds, but I feel (wrongly ?) uncomfortable operating the Fets in such a a region (see Id=F(Vds) curve in datasheet). I might be wrong in that, but, as you can trim the cascode bias voltage, feel free to try different cascode bias up to 10V for drain voltage, and see what you prefer.

Cheers