Decoupling

[richie00boy]

If you are decoupling an IC power pin to ground using a capacitor, why all the fuss about locating the cap physically close to the chip? If the trace returning to ground is not that short then surely it doesn't matter where on the trace the cap goes? Please make the assumption that due to constraints it's not possible to get the gnd trace any closer.

[pinkmouse]

Ritchie, you have to remember that all traces have resistance, inductance and capacitance. You can't take this out of the design equation, so you minimise it by reducing critical tracks to the minimum possible. If you can't fit the decoupling caps on the top, can't you sneak them in on the bottom?

edit: I always start a PCB design with ICs by laying out the power supply rails and grounds, it makes everything else so much easier.

[Nordic]

Decoupling caps tend to be tiny (I love those little red Wimas).
Putting them right on the pin allows you to move larger supply caps further away from the chip itself. Even a few millimeters of trace length could totaly nulify the effect of a decoupling cap. The length of the pin on the ground side is almost irrelivant as it forms part of the ground rail. If you can, you could try soldering directly to chips legs...

This is part of why we are now able to make very fast computers... Surface mount tech, has made possible decoupling caps smaller and smaller and one can get them right to the pin with no leads. The very same circuit built with conventional through hole components would simply not work because of trace lenghts and component lead lenghts...

[richie00boy]

pinkmouse,

I too generally start laying out with power first. However in this instance due to constraints, there wil either be a longish track from the IC pin to the cap which is then direct to ground, or I can put the cap right on the IC pin and have a longish track back to ground. My point is that both are identical in function, so why all the fuss about soldering direct to pins etc?

Nordic,

Thanks, but I think you didn't quite get my point. Hopefully I've made it clearer now.

[pinkmouse]

The latter is the best solution. Decoupling is basically to stop hash getting into the chip. If the cap is right by the pin, then the amount of connection distance that is influenced by capacitive or inductive input into that rail is minimised, whereas if it is at a distance, all that track is open to external influences, and the resistance of the track itself sets up a voltage gradient that means the cap doesn't work as effectively. This isn't spice, there is no such thing as a perfect conductor!

[richie00boy]

Yes I guess if you look at the power pin as being able to be influenced by stuff being picked up - a bit like a MOSFET gate - then I can see the argument for locating the cap close to the power pin.

[Nordic]

Like Mousey said. The trace itself is an inductor, so with enough mm of trace or leads, your chip to cap connection changes to a chip connected to an inductor conected to a cap, which is quite diffirent. on the other side of the cap is the ground rail regardless of its length.

[richie00boy]

Surely though as it's just parts in series, in your case it will just be a cap with an inductor back to ground. A wire has inductance and resistance, simply grounding one end doesn't absolve the wire from the laws of physics

[Nordic]

the trace on the other side of the cap IS the ground rail, whereas the trace on the chip side goes from the chip via the trace via the leg of the cap, into the body of the cap until it finaly meets the capacitor proper...

I have tried to find some more info and found a reasonable interesting interview on the topic

http://www.ultracad.com/articles/todd_h.pdf

it certainly adds another perspective in realtion to the spacing of planes...

[Nordic]

In order to understand the decoupling cap we need to understand what it does... it is a power reservoir of sorts, and any dips in supply voltage (ripple) will be filled in by the power in the caps...

Power Supply Isolation:

Let's start with the recognition that power and ground systems are usually inherently "clean." At least, that would seem to be a necessary condition for good system performance. So we start with a power supply system that has been designed to be adequate for the system in which it is going to be used.

If the power system is inherently "clean," how then does noise get into it'? And that is the insight that is necessary for good circuit layout. The purpose is NOT to keep noise on the power planes from getting into your circuit, the purpose is to keep circuit noise from getting onto the power planes. Once this concept is recognized, PCB layout can be viewed differently and more effectively

"Switching Transients: Consider what happens when the signal levels change at the inputs of a single IC logic chip. The change in state of the output levels can cause a corresponding change in the current requirements through the chip at the V+ and ground pins. Remember that current is the flow of electrons. Therefore, the change in current requirement is really a change in the "flow rate" of electrons. The "speed" at which this flow rate changes is measured by the rise time of the chip.

Therefore, for example, for a chip with a 1.0 nsec rise time, the flow rate of electrons (the current) must change from the old level to the new level in about 1.0 nsec. That's pretty fast!

For cases where the current requirement increases, the additional current is supplied through the power and ground planes. In a normal, steady state analysis, this poses no problem whatsoever. But what happens in the first few nanoseconds? The power and ground planes have considerable inductance associated with them, and they simply cannot respond with additional charge (electron flow) that fast. So we have two mutually exclusive requirements: (a) a logic chip that requires additional electron flow (current) in about a nanosecond or so, and
(b) a source (power and ground plane) that simply cannot supply electron flow that fast.


What happens under these circumstances is not always predictable. Some of the possible results are:

Timing Errors: The chip simply may slow down and switch only as fast as charge can be supplied. This can result in logic timing problems and logic errors due to logic state uncertainty.

Noise Error: Current supply may not be sufficient to support output levels. So, output levels may fall out of specification and noise margins significantly decrease, resulting in logic level uncertainty and logic errors.