Help troubleshooting active crossover

[drfrink24]

Hello all. Mr. Price is probably knee deep with finals at MIT this week, so, I thought I'd post this question here, see if anyone with more knowledge than me can help (aka everyone).

Here is the problem. For both low-pass R/L filters, without a source input, I'm seeing DC offset start at 5.0v, and steadily climb past 10v, presumably, it will keep climbing.

I've attached the scematic and link for more information. Does anyone have any ideas? The HP L/R is steady at .03v for each channel. The regulated and unregulated power supply values check out as well. Thanks for any and all input.


Link to website

[tiroth]

DC at input, or DC at gates of stage 1 and/or 2 of LP. There are series caps in HP to prevent this.

I'm guessing current sources are designed for 0 volts on output (if not then design error?), so perhaps there is an odd transistor that is pretty far off.

[tiroth]

Ah, one more thought. Operating point is dependent on supply voltage, might check that too.

[richie00boy]

Shouldn't there be a method of DC bias on the input? I know fets don't need a bias as such, but with not being tied to anything at DC the gate will simply drift through leakage capacitance due to Cgate and C101.

[Frank Berry]

Originally posted by richie00boy
Shouldn't there be a method of DC bias on the input? I know fets don't need a bias as such, but with not being tied to anything at DC the gate will simply drift through leakage capacitance due to Cgate and C101.

Absolutely. There must be a path to ground on the input.

[drfrink24]

Originally posted by tiroth
DC at input, or DC at gates of stage 1 and/or 2 of LP. There are series caps in HP to prevent this.

I'm guessing current sources are designed for 0 volts on output (if not then design error?), so perhaps there is an odd transistor that is pretty far off.

According to Mr. Price, with an input source, there is supposed to be some small AC on output.

[tiroth]

If your source doesn't have a resistor to ground at the output, then I'd first tackle richie00boy's solution and see if that works.

[richie00boy]

The input scheme is quite bizarre IMO. As well as attenuating the input somewhat it also changes the frequency at which the lowpass rolloff occurs. As well as having no DC bias. Not exactly the example of best practice I'd expect from a MIT tutor!

[drfrink24]

Well, I'm a little confused then...

What some people are telling me here is, it very well may be a design flaw, and not something I screwed up, and they are suggesting adding to his design.

The original designer and supplier of this PCB, has been using this in his setup for a few months now. He's been helping me troubleshoot other problems, until recently when I assume he's become busy. I would think he would have discovered these design errors in his setup, and would have informed me of the changes by now.

The only changes I've been made aware of are adding output capacitors (.1uf) for the high-pass.

I would assume with a 10v DC offset that keeps climbing, I've done something terribly wrong, not a design flaw.

[richie00boy]

It's not a shining example of best practice IMO, but if connected to a source with DC coupled output then it will work fine. Maybe that's how it was intended to be used?

To troubleshoot if the floating input is a problem simply ground the input. If it stabilises then it's fine, if not then there's an error somewhere.