Hi everyone, I´ve got a question:
Should electrolytic caps be bypassed at the load or at the cap´s pins?
In my case it´s an output-decoupling 10000µF cap between FET and output; elect. cap´s pins or between FET´s leg and output-pin?
And if I have several electrolytic caps (3*10000µF80V) in parallel, where do I bypass then? There where I take the supply voltage from and ground? Well, can´t bypass individually, these 1,5µF film caps aren´t that cheap...
Thank y'all, David
Should electrolytic caps be bypassed at the load or at the cap´s pins?
In my case it´s an output-decoupling 10000µF cap between FET and output; elect. cap´s pins or between FET´s leg and output-pin?
And if I have several electrolytic caps (3*10000µF80V) in parallel, where do I bypass then? There where I take the supply voltage from and ground? Well, can´t bypass individually, these 1,5µF film caps aren´t that cheap...
Thank y'all, David
bypassing an electrolytic, at least to my way of thinking, compensates for the ESL of the capacitor, in that an electrolytic has a higher impedance at high frequencies due to the series inductance. so you could bypass one time near the electrolytic with a 100nF film capacitor at the power supply.
it's not really "bypassing", rather "decoupling" but place, as close as possible to the chip being driven -- with 100nF or 10nF ceramics on each of the power pins. these "bypass" caps decouple the power supply lines, removing whatever RFI, EMI nasties may have been picked up along the way.
fwiw, National shows the power pins of the LM4780 decoupled with 10u and 100n capacitors.
it's not really "bypassing", rather "decoupling" but place, as close as possible to the chip being driven -- with 100nF or 10nF ceramics on each of the power pins. these "bypass" caps decouple the power supply lines, removing whatever RFI, EMI nasties may have been picked up along the way.
fwiw, National shows the power pins of the LM4780 decoupled with 10u and 100n capacitors.
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